US Patent Application 18124094. MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF simplified abstract

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MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF

Organization Name

Samsung Electronics Co., Ltd.


Inventor(s)

Duhwi Kim of Suwon-si (KR)


Junghak Song of Suwon-si (KR)


Chanho Lee of Suwon-si (KR)


MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18124094 Titled 'MEMORY DEVICE INCLUDING MULTI-BIT CELL AND OPERATING METHOD THEREOF'

Simplified Explanation

This abstract describes a memory device that consists of multiple multi-bit cells. Each multi-bit cell is connected to a column selection line, several write word lines, and several read word lines. The device also includes an input circuit that generates a signal for writing data into the multi-bit cells. Each multi-bit cell has a latch circuit that receives and stores the input signal when a write word line is activated, and releases the stored signal when the write word line or column selection line is deactivated. Additionally, there is a read circuit that retrieves the stored signal from the latch circuit and outputs it to a bit line when a read word line is activated.


Original Abstract Submitted

A memory device includes a plurality of multi-bit cells, wherein each of the plurality of multi-bit cells includes a plurality of bit cells commonly connected to a column selection line, respectively connected to a plurality of write word lines, and respectively connected to a plurality of read word lines and an input circuit configured to provide a first signal corresponding to a bit to be written, to the plurality of bit cells, wherein each of the plurality of bit cells includes a latch circuit configured to receive the first signal in response to a write word line being activated and latch the first signal in response to the write word line being deactivated or a column selection line being deactivated, and a read circuit configured to output the first signal stored in the latch circuit to a bit line in response to a read word line being activated.