US Patent Application 17965551. 3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL LAYER INTERVALS AT LOWER NANOSHEET TRANSISTOR AND UPPER NANOSHEET TRANSISTOR simplified abstract
3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL LAYER INTERVALS AT LOWER NANOSHEET TRANSISTOR AND UPPER NANOSHEET TRANSISTOR
Organization Name
Inventor(s)
Gunho Jo of Schenectady NY (US)
Byounghak Hong of Latham NY (US)
Seungchan Yun of Waterford NY (US)
Jaejik Baek of Watervliet NY (US)
3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL LAYER INTERVALS AT LOWER NANOSHEET TRANSISTOR AND UPPER NANOSHEET TRANSISTOR - A simplified explanation of the abstract
This abstract first appeared for US patent application 17965551 titled '3D-STACKED SEMICONDUCTOR DEVICE HAVING DIFFERENT CHANNEL LAYER INTERVALS AT LOWER NANOSHEET TRANSISTOR AND UPPER NANOSHEET TRANSISTOR
Simplified Explanation
The patent application describes a multi-stack semiconductor device consisting of two nanosheet transistors.
The first transistor, called the lower nanosheet transistor, is composed of multiple lower channel layers surrounded by a gate structure.
The second transistor, known as the upper nanosheet transistor, is stacked on top of the lower nanosheet transistor and comprises multiple upper channel layers surrounded by the same gate structure.
The key innovation is that the lower channel layers in the lower nanosheet transistor have a smaller channel interval compared to the upper channel layers in the upper nanosheet transistor.
Bullet points:
- The patent application presents a multi-stack semiconductor device with two nanosheet transistors. - The lower nanosheet transistor consists of multiple lower channel layers surrounded by a gate structure. - The upper nanosheet transistor is stacked on top of the lower nanosheet transistor and comprises multiple upper channel layers surrounded by the same gate structure. - The lower channel layers have a smaller channel interval than the upper channel layers. - This innovation aims to enhance the performance and efficiency of the semiconductor device.
Original Abstract Submitted
Provided is a multi-stack semiconductor device that includes: a lower nanosheet transistor including a plurality of lower channel layers surrounded by a gate structure; and an upper nanosheet transistor stacked on the lower nanosheet transistor and including a plurality of upper channel layers surrounded by the gate structure, wherein the lower channel layers have a smaller channel interval than the upper channel layers.
