Difference between revisions of "SAMSUNG ELECTRONICS CO., LTD. patent applications published on December 28th, 2023"

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'''Summary of the patent applications from SAMSUNG ELECTRONICS CO., LTD. on December 28th, 2023'''
 
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Samsung Electronics Co., Ltd. has filed several recent patents related to semiconductor devices and integrated circuits. These patents describe various structures and technologies aimed at improving the performance, efficiency, and integration of electronic devices.
 
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Summary:
 
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- The patents include technologies such as heterocyclic compounds, stacked structures in integrated circuit devices, three-dimensional semiconductor memory devices, stacked semiconductor dies in a package, 3D semiconductor memory devices, memory cell structures with compact layouts, and semiconductor devices with memory cell structures and through wiring regions.
 
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- The technologies address challenges such as limited memory capacity, efficient stacking of semiconductor dies, integration of memory and computing blocks, increased storage capacity, improved performance and reliability, and efficient layout of semiconductor devices.
 
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- The benefits of these technologies include higher memory capacity, faster access times, improved performance and efficiency, space-saving designs, simplified manufacturing processes, and enhanced overall device performance.
 
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Notable Applications:
 
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- Memory devices for computers, smartphones, and other electronic devices.
 
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- Integrated circuits for data processing, memory storage, and signal amplification.
 
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- Power management systems for efficient energy usage.
 
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- High-density storage devices for data centers and cloud computing.
 
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- Non-volatile memory for automotive and aerospace applications.
 
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- Semiconductor packaging for electronic devices.
 
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- Memory and computing integration in a single package.
 
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- Various electronic devices such as smartphones, tablets, and computers.
 
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* Heterocyclic compounds.
 
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* Stacked structures in integrated circuit devices.
 
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* Three-dimensional semiconductor memory devices.
 
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* Stacked semiconductor dies in a package.
 
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* 3D semiconductor memory devices.
 
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* Memory cell structures with compact layouts.
 
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* Semiconductor devices with memory cell structures and through wiring regions.
 
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==Patent applications for SAMSUNG ELECTRONICS CO., LTD. on December 28th, 2023==
 
==Patent applications for SAMSUNG ELECTRONICS CO., LTD. on December 28th, 2023==
  
Line 1,174: Line 1,144:
 
Kiseok LEE
 
Kiseok LEE
  
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'''Brief explanation'''
 
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The patent application describes a semiconductor device that includes a cell active pattern, a gate structure, a bit-line contact, a connection pattern, and a cell separation pattern.
 
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* The cell active pattern consists of two portions that are spaced apart from each other.
 
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* The gate structure is located between the two portions of the cell active pattern.
 
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* The bit-line contact is positioned on the first portion of the cell active pattern.
 
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* The connection pattern is located on the second portion of the cell active pattern.
 
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* The cell separation pattern is in contact with both the bit-line contact and the connection pattern.
 
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* The cell separation pattern has two sidewalls, with the first sidewall in contact with the connection pattern and the second sidewall in contact with the bit-line contact.
 
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* The upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, while the lower portion is spaced apart from the bit-line contact.
 
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Potential applications of this technology:
 
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* Semiconductor manufacturing
 
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* Integrated circuit design
 
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* Memory devices
 
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Problems solved by this technology:
 
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* Provides a structure for efficient cell separation in a semiconductor device
 
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* Helps to prevent interference between different portions of the cell active pattern
 
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Benefits of this technology:
 
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* Improved performance and reliability of semiconductor devices
 
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* Enhanced manufacturing efficiency and yield
 
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'''Abstract'''
 
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A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.
 
  
 
===SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[18149800. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18149800]])===
 
===SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[18149800. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18149800]])===
Line 1,212: Line 1,152:
 
Jonghyeok KIM
 
Jonghyeok KIM
  
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'''Brief explanation'''
 
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The patent application describes a semiconductor memory device with specific patterns and structures to improve its performance and functionality. Here is a simplified explanation of the abstract:
 
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* The semiconductor memory device includes an active pattern defined by a device isolation pattern, which helps isolate different components of the device.
 
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* A bit line extends in a first direction on the device isolation pattern and the active pattern, allowing for the transfer of data within the memory device.
 
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* A bit line capping pattern is stacked on top of the bit line and includes three sequentially stacked patterns: a first capping pattern, a second capping pattern, and a third capping pattern. These patterns provide additional protection and functionality to the bit line.
 
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* A shield pattern is also included, covering one side of the bit line. The upper surface of the shield pattern is positioned at a lower height than the upper surface of the first capping pattern, ensuring proper functionality and performance of the memory device.
 
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Potential applications of this technology:
 
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* Semiconductor memory devices are widely used in various electronic devices, including computers, smartphones, and tablets. This innovation can enhance the performance and functionality of these devices.
 
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* The improved memory device can be utilized in data centers and servers, where high-speed and reliable memory is crucial for efficient data processing and storage.
 
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Problems solved by this technology:
 
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* The specific patterns and structures described in the patent application address issues related to data transfer, isolation, and protection within a semiconductor memory device.
 
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* By optimizing the positioning and stacking of the capping and shield patterns, the patent application aims to improve the overall performance and reliability of the memory device.
 
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Benefits of this technology:
 
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* The semiconductor memory device with the described patterns and structures can offer faster data transfer rates and improved data integrity.
 
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* The optimized capping and shield patterns provide enhanced protection against external interference and noise, resulting in more reliable memory operations.
 
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* The innovation can potentially lead to more efficient and compact memory devices, allowing for increased memory capacity in smaller form factors.
 
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'''Abstract'''
 
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A semiconductor memory device including an active pattern defined by a device isolation pattern, a bit line extending in a first direction on the device isolation pattern and the active pattern, a bit line capping pattern including a first capping pattern, a second capping pattern, and a third capping pattern sequentially stacked on an upper surface of the bit line, and a shield pattern covering one side of the bit line may be provided. An upper surface of the shield pattern may be at a height lower than an upper surface of the first capping pattern.
 
  
 
===SEMICONDUCTOR DEVICES ([[18192329. SEMICONDUCTOR DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18192329]])===
 
===SEMICONDUCTOR DEVICES ([[18192329. SEMICONDUCTOR DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18192329]])===
Line 1,247: Line 1,160:
 
Jongmin KIM
 
Jongmin KIM
  
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'''Brief explanation'''
 
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The patent application describes a semiconductor device with a specific structure involving contact plugs, spacer structures, and bit line structures.
 
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* The device includes a first contact plug structure on a substrate, a lower spacer structure on the sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure.
 
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* The first contact plug structure consists of a conductive pad, an ohmic contact pattern, and a conductive filling pattern.
 
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* The conductive filling pattern is made of metal and has a lower portion with a wider width and an upper portion with a narrower width.
 
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* The lower spacer structure is in contact with the sidewall of the conductive filling pattern.
 
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Potential applications of this technology:
 
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* This semiconductor device structure can be used in various electronic devices such as smartphones, computers, and tablets.
 
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* It can be applied in memory devices, logic circuits, and other semiconductor components.
 
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Problems solved by this technology:
 
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* The specific structure of the device helps to improve the performance and efficiency of the semiconductor device.
 
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* It provides a more reliable and stable connection between the different components of the device.
 
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Benefits of this technology:
 
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* The improved performance and efficiency of the semiconductor device can lead to faster and more reliable electronic devices.
 
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* The stable connection between components enhances the overall durability and lifespan of the device.
 
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'''Abstract'''
 
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A semiconductor device including a first contact plug structure on a substrate, a lower spacer structure on a sidewall of the first contact plug structure, and a bit line structure on the first contact plug structure and including a conductive structure and an insulation structure stacked in a vertical direction substantially perpendicular to an upper surface of the substrate may be provided. The first contact plug structure may include a conductive pad contacting the upper surface of the substrate, an ohmic contact pattern on the conductive pad, and a conductive filling pattern on the ohmic contact pattern. The conductive filling pattern may include metal, and include a lower portion having a relatively large width and an upper portion having a relatively small width. The lower spacer structure may contact a sidewall of the conductive filling pattern.
 
  
 
===SEMICONDUCTOR DEVICES ([[18464668. SEMICONDUCTOR DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18464668]])===
 
===SEMICONDUCTOR DEVICES ([[18464668. SEMICONDUCTOR DEVICES simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18464668]])===
Line 1,281: Line 1,168:
 
Youngwoo Kim
 
Youngwoo Kim
  
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'''Brief explanation'''
 
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The abstract describes a semiconductor device that includes a substrate with two regions, insulating patterns in the second region that define active patterns, gate electrodes stacked on the substrate, separation regions in contact with the active patterns, and channel structures penetrating through the gate electrodes in the first region. At least one of the separation regions is in contact with the substrate below the insulating patterns.
 
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* The semiconductor device has a substrate with two distinct regions.
 
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* Insulating patterns are present in the second region and define active patterns of the substrate.
 
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* Gate electrodes are stacked on the substrate and spaced apart from each other, extending in a specific direction.
 
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* First separation regions are in contact with the active patterns and extend in the same direction as the gate electrodes.
 
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* Second separation regions are located between the first separation regions in the same direction.
 
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* Channel structures penetrate through the gate electrodes in the first region.
 
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* At least one of the second separation regions is in contact with the substrate below the insulating patterns.
 
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== Potential Applications ==
 
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* This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
 
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* It can be utilized in the manufacturing of integrated circuits and microprocessors.
 
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* The device can be employed in the development of advanced sensors and communication systems.
 
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== Problems Solved ==
 
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* The device solves the problem of efficiently separating active patterns and gate electrodes in a semiconductor device.
 
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* It addresses the challenge of creating channel structures that penetrate through the gate electrodes.
 
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* The device solves the issue of ensuring proper contact between the separation regions and the substrate below the insulating patterns.
 
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== Benefits ==
 
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* The semiconductor device provides improved performance and functionality in electronic devices.
 
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* It allows for more efficient manufacturing processes for integrated circuits and microprocessors.
 
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* The device enables the development of smaller and more advanced electronic components.
 
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'''Abstract'''
 
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A semiconductor device includes a substrate having a first region and a second region, insulating patterns in the substrate in the second region that define active patterns of the substrate, gate electrodes spaced apart from each other and stacked on an upper surface of the substrate and extending in a first direction, first separation regions extending in the first direction and in contact with the active patterns, second separation regions extending between the first separation regions in the first direction, and channel structures penetrating through the gate electrodes in the first region. At least one of the second separation regions is in contact with the substrate below the insulating patterns.
 
  
 
===SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME ([[18190876. SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18190876]])===
 
===SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME ([[18190876. SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18190876]])===
Line 1,318: Line 1,176:
 
Donghoon KWON
 
Donghoon KWON
  
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'''Brief explanation'''
 
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The abstract describes a semiconductor device with various components and structures, including circuit devices, interconnection lines, insulating layers, source structures, gate electrodes, channel structures, contact plugs, and spacer layers.
 
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* The semiconductor device includes a substrate and circuit devices on the substrate.
 
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* Lower interconnection lines are electrically connected to the circuit devices.
 
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* A peripheral region insulating layer covers the lower interconnection lines.
 
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* A source structure is located on the peripheral region insulating layer.
 
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* Gate electrodes are stacked and spaced apart from each other in a first direction on the source structure.
 
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* Channel structures penetrate through the gate electrodes and each include a channel layer.
 
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* Contact plugs penetrate through the gate electrodes and the source structure, extending in the first direction, and are connected to a portion of the lower interconnection lines.
 
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* Spacer layers are located between the contact plugs and the source structure and are made of a different material than the insulating layer in the peripheral region.
 
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* Each spacer layer has a first width on an upper surface and a second width greater than the first width on a lower surface.
 
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Potential applications of this technology:
 
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* Semiconductor devices used in various electronic devices such as smartphones, computers, and tablets.
 
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* Integrated circuits for data processing, memory storage, and signal amplification.
 
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* Power management systems for efficient energy usage.
 
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Problems solved by this technology:
 
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* Provides improved electrical connectivity and insulation between different components of the semiconductor device.
 
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* Helps in reducing signal interference and noise.
 
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* Enhances the overall performance and reliability of the semiconductor device.
 
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Benefits of this technology:
 
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* Higher efficiency and performance of the semiconductor device.
 
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* Improved signal transmission and reduced signal loss.
 
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* Enhanced reliability and durability of the device.
 
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* Enables miniaturization and integration of complex circuitry.
 
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'''Abstract'''
 
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A semiconductor device includes a substrate, circuit devices on the substrate, lower interconnection lines electrically connected to the circuit devices, a peripheral region insulating layer covering the lower interconnection lines, a source structure on the peripheral region insulating layer, gate electrodes stacked and spaced apart from each other in a first direction on the source structure, channel structures penetrating through the gate electrodes and each including a channel layer, contact plugs penetrating through the gate electrodes and the source structure, extending in the first direction, and connected to a portion of the lower interconnection lines, and spacer layers between the contact plugs and the source structure and including a material different from a material of the insulating layer in the peripheral region, wherein each of the spacer layers has a first width on an upper surface and has a second width greater than the first width on a lower surface.
 
  
 
===SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME ([[18202111. SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18202111]])===
 
===SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME ([[18202111. SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18202111]])===
Line 1,361: Line 1,184:
 
Seulji LEE
 
Seulji LEE
  
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'''Brief explanation'''
 
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The patent application describes a semiconductor device that includes a memory cell structure, a through wiring region, and a barrier structure. The memory cell structure consists of stacked gate electrodes and interlayer insulating layers, a channel structure, and isolation regions. The through wiring region includes stacked interlayer insulating layers and sacrificial insulating layers, as well as a through contact plug that connects to circuit devices. The sacrificial insulating layers have recess portions that are horizontally recessed from the barrier structure.
 
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* The semiconductor device includes a memory cell structure and a through wiring region.
 
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* The memory cell structure consists of stacked gate electrodes and interlayer insulating layers.
 
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* The through wiring region includes stacked interlayer insulating layers and sacrificial insulating layers.
 
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* The sacrificial insulating layers have recess portions that are horizontally recessed from the barrier structure.
 
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* The through contact plug connects to circuit devices and penetrates through the interlayer insulating layers and sacrificial insulating layers.
 
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==Potential Applications==
 
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* This technology can be applied in the manufacturing of semiconductor devices.
 
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* It can be used in various electronic devices such as computers, smartphones, and tablets.
 
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==Problems Solved==
 
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* The patent application addresses the need for improved semiconductor devices with memory cell structures and through wiring regions.
 
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* It solves the problem of efficiently connecting circuit devices in a semiconductor device.
 
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==Benefits==
 
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* The described semiconductor device provides an improved memory cell structure and through wiring region.
 
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* The recess portions in the sacrificial insulating layers allow for more efficient connection of circuit devices.
 
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* This technology can lead to enhanced performance and functionality of electronic devices.
 
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'''Abstract'''
 
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A semiconductor device includes: a memory cell structure on a peripheral circuit structure; a through wiring region on the peripheral circuit structure; and a barrier structure surrounding the through wiring region. The memory cell structure includes: gate electrodes and first interlayer insulating layers that are alternately stacked, the gate electrodes forming a step shape on the second region; a channel structure; and isolation regions penetrating through the gate electrodes. The through wiring region includes: second interlayer insulating layers and sacrificial insulating layers alternately stacked on the second region; and a through contact plug penetrating through the second interlayer insulating layers and the sacrificial insulating layers, and electrically connected to the circuit devices. Each of the sacrificial insulating layers includes a recess portion that is horizontally recessed from the barrier structure toward each of the sacrificial insulating layers.
 
  
 
===SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[18336497. SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18336497]])===
 
===SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[18336497. SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18336497]])===
Line 1,394: Line 1,192:
 
Seokcheon BAEK
 
Seokcheon BAEK
  
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'''Brief explanation'''
 
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The abstract describes a semiconductor device that includes a substrate with a memory cell region and a connection region. It also includes gate electrodes in the memory cell region, a pair of gate stack separation insulation layers, and a pad structure in the connection region.
 
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* The semiconductor device includes gate electrodes arranged in a vertical direction, including a ground selection line and multiple word lines.
 
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* The gate stack separation insulation layers pass through the gate electrodes and extend in a horizontal direction.
 
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* The pad structure in the connection region includes multiple pad layers connected to the gate electrodes.
 
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* The pad layers are arranged in a staircase shape in both horizontal directions.
 
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* The ground selection line includes multiple cut regions that are apart from the edges of the pad layers.
 
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Potential applications of this technology:
 
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* Memory devices: The semiconductor device can be used in memory devices such as flash memory or DRAM.
 
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* Integrated circuits: It can be utilized in various integrated circuits that require memory cell regions and connection regions.
 
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Problems solved by this technology:
 
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* Efficient layout: The staircase arrangement of the pad layers allows for a compact and efficient layout of the semiconductor device.
 
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* Gate stack separation: The gate stack separation insulation layers ensure proper isolation between the gate electrodes.
 
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Benefits of this technology:
 
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* Space-saving: The compact layout of the pad layers saves space on the semiconductor device.
 
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* Improved performance: The proper isolation between gate electrodes enhances the performance and reliability of the device.
 
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'''Abstract'''
 
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A semiconductor device is provided. The semiconductor device includes a substrate including a memory cell region and a connection region, a plurality of gate electrodes in the memory cell region and arranged apart from one another in a vertical direction, the gate electrodes including a ground selection line and a plurality of word lines, a pair of gate stack separation insulation layers passing through the gate electrodes and extending in a first horizontal direction in the memory cell region and the connection region, and a pad structure including a plurality of pad layers in the connection region, connected to respective ones of the gate electrodes, arranged in a staircase shape in the first horizontal direction and in a second horizontal direction, the ground selection line including a plurality of ground selection line cut regions each being apart from edges of the pad layers in the second horizontal direction.
 
  
 
===THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME ([[18171858. THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18171858]])===
 
===THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME ([[18171858. THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18171858]])===
Line 1,426: Line 1,200:
 
Jeon Il LEE
 
Jeon Il LEE
  
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'''Brief explanation'''
 
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The abstract describes a 3D semiconductor memory device that includes a structure with two conductive pillars, an electrode, a ferroelectric layer, and a channel layer. The ferroelectric layer extends between the conductive pillars and the electrode.
 
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* The 3D semiconductor memory device has a first through-structure with two conductive pillars and an electrode.
 
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* The ferroelectric layer is located between the electrode and the channel layer, extending from one conductive pillar to the other.
 
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* The channel layer connects the two conductive pillars.
 
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* The device is designed to store and retrieve data using the ferroelectric layer.
 
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== Potential Applications ==
 
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* Memory devices for computers, smartphones, and other electronic devices.
 
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* High-density storage devices for data centers and cloud computing.
 
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* Non-volatile memory for automotive and aerospace applications.
 
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−
== Problems Solved ==
 
−
* Increasing the storage capacity of semiconductor memory devices.
 
−
* Improving the performance and reliability of memory devices.
 
−
* Enabling 3D integration of memory cells for higher density and faster access.
 
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−
== Benefits ==
 
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* Higher storage capacity due to the 3D structure.
 
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* Faster access times and improved performance.
 
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* Non-volatile memory that retains data even when power is lost.
 
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'''Abstract'''
 
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A 3D semiconductor memory device includes a first through-structure on a substrate, the first through-structure comprising first and second conductive pillars spaced apart from each other in a first direction, an electrode adjacent to the first through-structure, the electrode horizontally extending in the first direction, and a ferroelectric layer and a channel layer between the electrode and the first and second conductive pillars. The channel layer connects the first and second conductive pillars to each other. The ferroelectric layer is disposed between the electrode and the channel layer. The ferroelectric layer extends from a sidewall of the first conductive pillar to a sidewall of the second conductive pillar along the channel layer when viewed in a plan view.
 
  
 
===STACK-TYPE SEMICONDUCTOR PACKAGE ([[18165412. STACK-TYPE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18165412]])===
 
===STACK-TYPE SEMICONDUCTOR PACKAGE ([[18165412. STACK-TYPE SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18165412]])===
Line 1,460: Line 1,208:
 
KYUNG DON MUN
 
KYUNG DON MUN
  
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−
'''Brief explanation'''
 
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The abstract describes a semiconductor package that includes multiple semiconductor dies stacked together. The package includes a buffer die, one or more first semiconductor dies, and a second semiconductor die. The second semiconductor die has a first layer with memory blocks and a second layer with computing blocks. The first and second layers are in contact with each other, and the memory blocks and computing blocks have pads that are also in contact with each other.
 
−
 
−
* A semiconductor package with stacked semiconductor dies
 
−
* Includes a buffer die, first semiconductor dies, and a second semiconductor die
 
−
* The second semiconductor die has a first layer with memory blocks and a second layer with computing blocks
 
−
* The first and second layers are in contact with each other
 
−
* The memory blocks and computing blocks have pads that are in contact with each other
 
−
 
−
== Potential Applications ==
 
−
* Semiconductor packaging for electronic devices
 
−
* Memory and computing integration in a single package
 
−
 
−
== Problems Solved ==
 
−
* Efficient stacking of semiconductor dies
 
−
* Integration of memory and computing blocks
 
−
 
−
== Benefits ==
 
−
* Compact and space-saving design
 
−
* Improved performance and efficiency in electronic devices
 
−
* Simplified manufacturing process
 
−
 
−
'''Abstract'''
 
−
A semiconductor package includes a buffer die. One or more first semiconductor dies are stacked on the buffer die such that active surfaces face the buffer die. A second semiconductor die is stacked on the first semiconductor dies. The second semiconductor die includes a first layer and a second layer disposed thereon. The first layer includes a first semiconductor substrate. First memory blocks are disposed on the first semiconductor substrate. A first penetration electrode vertically penetrates the first semiconductor substrate and is connected to the first memory blocks. The second layer includes a second semiconductor substrate and computing blocks disposed on the second semiconductor substrate. The first and second layers have active surfaces in contact with each other. The first memory block aid the computing block have first and second pads, respectively, in contact with each other.
 
  
 
===THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME ([[18180366. THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18180366]])===
 
===THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME ([[18180366. THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18180366]])===
Line 1,493: Line 1,216:
 
Jiwon Kim
 
Jiwon Kim
  
−
 
−
'''Brief explanation'''
 
−
The abstract describes a three-dimensional semiconductor memory device that includes a stacked structure with gate electrodes, a source structure, and a second substrate. The source structure consists of two conductive patterns, one between the second substrate and the stacked structure and the other on top of the first conductive pattern. The second conductive pattern has three parts: one between the first conductive pattern and the second substrate, a connection part passing through the second substrate, and a second part on the second substrate connected to the first part through the connection part.
 
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−
* The semiconductor memory device has a three-dimensional structure with stacked gate electrodes and a source structure.
 
−
* The source structure includes two conductive patterns, providing a more efficient and compact design.
 
−
* The second conductive pattern has three parts, allowing for better connectivity and integration with the first conductive pattern and the second substrate.
 
−
 
−
==Potential Applications==
 
−
* This technology can be used in various electronic devices that require high-density memory storage, such as smartphones, tablets, and computers.
 
−
* It can also be applied in data centers and cloud computing facilities to enhance memory capacity and performance.
 
−
 
−
==Problems Solved==
 
−
* The three-dimensional structure of the semiconductor memory device solves the problem of limited memory capacity in traditional two-dimensional memory devices.
 
−
* The compact design and improved connectivity of the source structure address the challenges of increasing memory density while maintaining efficient operation.
 
−
 
−
==Benefits==
 
−
* The three-dimensional structure allows for higher memory capacity and performance compared to traditional memory devices.
 
−
* The compact design and improved connectivity result in a smaller footprint and more efficient use of space.
 
−
* The technology enables faster data access and processing, enhancing overall device performance.
 
−
 
−
'''Abstract'''
 
−
A three-dimensional semiconductor memory device includes a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a stacked structure including gate electrodes extending in a first direction, a source structure on the stacked structure, and a second substrate in contact with the source structure. The source structure includes a first source conductive pattern between the second substrate and the stacked structure and a second source conductive pattern on the first source conductive pattern. The second source conductive pattern includes a first source part between the first source conductive pattern and the second substrate, a source connection part passing through the second substrate and extending in the first direction, and a second source part on the second substrate and connected to the first source part through the source connection part.
 
  
 
===INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[18337180. INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18337180]])===
 
===INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME ([[18337180. INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18337180]])===
Line 1,524: Line 1,224:
 
Seokcheon Baek
 
Seokcheon Baek
  
−
 
−
'''Brief explanation'''
 
−
The abstract describes an integrated circuit device that consists of two stacked structures. The first structure includes a substrate, a peripheral circuit, and a bonding pad. The second structure includes a substrate with gate electrodes, a cell contact plug, a node separation structure, and a bonding pad.
 
−
 
−
* The first structure of the integrated circuit device includes a substrate, peripheral circuit, and bonding pad.
 
−
* The second structure is stacked on top of the first structure and includes a substrate with gate electrodes.
 
−
* A cell contact plug is connected to the gate electrodes and is insulated from other gate electrodes.
 
−
* A node separation structure surrounds the upper part of the cell contact plug.
 
−
* A bonding pad is used to connect the first and second structures.
 
−
 
−
== Potential Applications ==
 
−
* This integrated circuit device can be used in various electronic devices, such as smartphones, computers, and IoT devices.
 
−
* It can be utilized in the manufacturing of microprocessors, memory chips, and other integrated circuits.
 
−
 
−
== Problems Solved ==
 
−
* The integration of multiple structures in a compact and efficient manner is a challenge in the design and manufacturing of integrated circuits.
 
−
* This technology solves the problem of connecting and insulating gate electrodes in a stacked structure.
 
−
 
−
== Benefits ==
 
−
* The stacked structure allows for a higher level of integration, enabling more complex and powerful integrated circuits.
 
−
* The use of a cell contact plug and node separation structure improves the electrical performance and reliability of the device.
 
−
* The bonding pads facilitate the connection between different structures, ensuring proper functionality of the integrated circuit.
 
−
 
−
'''Abstract'''
 
−
An integrated circuit device includes a first structure and a second structure stacked on the first structure. The first structure includes a first substrate, a peripheral circuit, and a first bonding pad. The second structure includes a second substrate that includes a first side and a second side, a plurality of gate electrodes disposed on the first side of the second substrate, a first cell contact plug that penetrates a first conductive pad of a first gate electrode, is electrically connected to the first gate electrode, penetrates second gate electrodes disposed above the first gate electrode, and is electrically insulated from the second gate electrodes, a first node separation structure that penetrates the second substrate and surrounds an upper part of the first cell contact plug positioned in the second substrate, and a second bonding pad bonded to the first bonding pad.
 
  
 
===HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME ([[18242050. HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18242050]])===
 
===HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME ([[18242050. HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)|18242050]])===
Line 1,556: Line 1,231:
  
 
Eunsuk Kwon
 
Eunsuk Kwon
−
 
−
 
−
'''Brief explanation'''
 
−
The abstract of the patent application describes a heterocyclic compound represented by Formula 1.
 
−
 
−
* The compound is a heterocyclic compound.
 
−
* It is represented by Formula 1.
 
−
* The abstract does not provide further details about the compound or its specific properties.
 
−
 
−
== Potential Applications ==
 
−
The potential applications of this technology are not specified in the abstract.
 
−
 
−
== Problems Solved ==
 
−
The problems solved by this technology are not specified in the abstract.
 
−
 
−
== Benefits ==
 
−
The benefits of this technology are not specified in the abstract.
 
−
 
−
'''Abstract'''
 
−
A heterocyclic compound represented by Formula 1:
 

Revision as of 05:51, 1 January 2024

Contents

Patent applications for SAMSUNG ELECTRONICS CO., LTD. on December 28th, 2023

SHOE CARE APPARATUS AND CONTROL METHOD THEREFOR (18241711)

Main Inventor

Joongwon NA


ELECTRONIC DEVICE AND METHOD OF ESTIMATING BODY TEMPERATURE USING THE SAME (17991123)

Main Inventor

Sungho KIM


ELECTRONIC DEVICE AND METHOD OF ESTIMATING BODY TEMPERATURE USING THE SAME (18155465)

Main Inventor

Sungho KIM


DEVICE FOR PROVIDING INFORMATION FOR IMPROVING SLEEP QUALITY AND METHOD THEREOF (18244064)

Main Inventor

Minseok CHOI


WEARING MODULE AND MOTION ASSISTANCE APPARATUS COMPRISING SAME (18463809)

Main Inventor

Minhyung LEE


POLISHING APPARATUS FOR A SUBSTRATE AND POLISHING METHOD FOR A SUBSTRATE USING THE SAME (18097540)

Main Inventor

Donghoon Kwon


SUBSTRATE POLISHING APPARATUS AND METHOD OF POLISHING SUBSTRATE USING THE SAME (18210107)

Main Inventor

Donghoon Kwon


METHOD FOR PRODUCING INJECTION-MOLDED ARTICLE AND ELECTRONIC DEVICE COMPRISING INJECTION-MOLDED ARTICLE (18465525)

Main Inventor

Chunghyo JUNG


HOUSING INCLUDING BIOMATERIAL AND ELECTRONIC DEVICE INCLUDING THE SAME (18186513)

Main Inventor

Hyunjung JUNG


WASHING MACHINE AND CONTROLLING METHOD OF WASHING MACHINE (18207927)

Main Inventor

Youngjin CHO


WASHING MACHINE AND CONTROLLING METHOD OF WASHING MACHINE (18211885)

Main Inventor

Dongpil SEO


DISPLAY APPARATUS (18133649)

Main Inventor

Jaeneung LEE


RANGE HOOD (18315087)

Main Inventor

Seokang KIM


ELECTRONIC DEVICE FOR IDENTIFYING MOVING DIRECTION OF ELECTRONIC DEVICE, AND OPERATING METHOD FOR ELECTRONIC DEVICE (18463599)

Main Inventor

Dukhyun CHANG


TERAHERTZ PROBE (18134731)

Main Inventor

Martin Priwisch


TRAINING METHOD AND TEST APPARATUS USING THE SAME (18158181)

Main Inventor

Kwang Kyu KIM


WIRELESS RECEIVE SIGNAL STRENGTH INDICATOR (RSSI)-BASED POSITIONING (17930644)

Main Inventor

Tianwei Xing


SYSTEM AND METHOD FOR MEASURING PROXIMITY BETWEEN DEVICES USING ACOUSTICS (17931455)

Main Inventor

Wenjun Jiang


DISPLAY APPARATUS FOR PROVIDING EXPANDED VIEWING WINDOW (18466664)

Main Inventor

Jong-Young Hong


DISPLAY DEVICE (18244637)

Main Inventor

Yeonkyun PARK


CAMERA MODULE AND ELECTRONIC DEVICE COMPRISING SAME (18463662)

Main Inventor

Youngjae HWANG


DEVELOPING APPARATUS (18199035)

Main Inventor

Sungki LEE


ELECTRONIC DEVICE (18462807)

Main Inventor

Hunyoung RYU


ELECTRONIC DEVICE AND CONTROLLING METHOD OF ELECTRONIC DEVICE (18222768)

Main Inventor

Haedong YEO


COOKING APPARATUS AND METHOD FOR CONTROLLING THEREOF (18219393)

Main Inventor

Haedong YEO


LITHOGRAPHY MODEL GENERATING METHOD BASED ON DEEP LEARNING, AND MASK MANUFACTURING METHOD INCLUDING THE LITHOGRAPHY MODEL GENERATING METHOD (18106091)

Main Inventor

Sangchul Yeo


FOLDABLE ELECTRONIC DEVICE INCLUDING ANTENNA (18243464)

Main Inventor

Jaeyoung HUH


FOLDABLE ELECTRONIC DEVICE INCLUDING HINGE LOCKING STRUCTURE (18190632)

Main Inventor

Minsu RHEE


STORAGE SYSTEMS INCLUDING A PLURALITY OF SOLID STATE DRIVES AND MANAGEMENT METHODS THEREOF (18076616)

Main Inventor

Heeseok Eun


MEMORY ACCESS METHOD AND DEVICE FOR A NUMA SYSTEM (18340122)

Main Inventor

YUEHUA DAI


SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME (18136915)

Main Inventor

Jongcheol Kim


MEMORY DEVICE, METHOD OF CALIBRATING SIGNAL LEVEL THEREOF, AND MEMORY SYSTEM HAVING THE SAME (18243350)

Main Inventor

Youngdo Um


STORAGE DEVICE AND OPERATING METHOD THEREOF (18139719)

Main Inventor

Hyunjoon Yoo


ELECTRONIC DEVICE AND METHOD FOR RECOGNIZING AUDIO OUTPUT DEVICE CONNECTED TO USB TYPE-C CONNECTOR (18243431)

Main Inventor

Wookwang LEE


ELECTRONIC APPARATUS AND CONTROL METHOD THEREFOR (18367345)

Main Inventor

Jiyoun KIM


STATIC CMOS-BASED FULL ADDER CIRCUITS (17821763)

Main Inventor

Debojyoti Banerjee


COMPILATION METHOD AND APPARATUS WITH NEURAL NETWORK (18464044)

Main Inventor

Hanwoong JUNG


COMPUTING DEVICE FOR HANDLING TASKS IN A MULTI-CORE PROCESSOR, AND METHOD FOR OPERATING COMPUTING DEVICE (18243477)

Main Inventor

Young Tae LEE


ELECTRONIC DEVICE AND CLIPBOARD OPERATION METHOD THEREOF (18463675)

Main Inventor

Youngjae MEEN


Privileged Firmware Mode Protection (17968182)

Main Inventor

Baibhav Singh


ELECTRONIC DEVICE AND METHOD FOR INPUTTING DATA INTO DATA ENTRY FIELD IN ELECTRONIC DEVIC (18244095)

Main Inventor

Kangmin LEE


ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF (18466469)

Main Inventor

Krzysztof ARENDT


ELECTRONIC APPARATUS AND CONTROLLING METHOD THEREOF (18134397)

Main Inventor

Sihyun Park


METHOD AND DEVICE FOR CORRECTING IMAGE ON BASIS OF COMPRESSION QUALITY OF IMAGE IN ELECTRONIC DEVICE (18241637)

Main Inventor

Kyuwon KIM


METHODS AND DEVICES FOR VIDEO RENDERING FOR VIDEO SEE-THROUGH (VST) AUGMENTED REALITY (AR) (18055304)

Main Inventor

Yingen Xiong


ELECTRONIC DEVICE FOR IMPROVING QUALITY OF IMAGE AND METHOD FOR IMPROVING QUALITY OF IMAGE BY USING SAME (18244088)

Main Inventor

Jungmin LEE


DISPLAY DEVICE INCLUDING LIGHT-EMITTING DIODE BACKLIGHT UNIT (18463914)

Main Inventor

Byungil KIM


PERSONALIZED MULTI-MODAL SPOKEN LANGUAGE IDENTIFICATION (17937692)

Main Inventor

Divya Neelagiri


SYSTEM AND METHOD FOR SPEAKER VERIFICATION FOR VOICE ASSISTANT (18047609)

Main Inventor

Myungjong Kim


ONLINE SPEAKER DIARIZATION USING LOCAL AND GLOBAL CLUSTERING (18046041)

Main Inventor

Myungjong Kim


MEMORY DEVICE AND REFRESH METHOD THEREOF (18197084)

Main Inventor

EUN AE LEE


SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME (18196703)

Main Inventor

Jongcheol Kim


SENSE AMPLIFIER CIRCUIT, MEMORY DEVICE INCLUDING THE SAME AND SENSING METHOD OF MEMORY DEVICE (18045846)

Main Inventor

Changyoung Lee


APPLICATION PROCESSORS AND ELECTRONIC DEVICES INCLUDING THE SAME (18462928)

Main Inventor

Kyumin Park


MEMORY CHIP AND MEMORY SYSTEM INCLUDING THE SAME (18189756)

Main Inventor

Kwangsook NOH


NONVOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING READ OPERATION OF THE SAME (18099808)

Main Inventor

Taeyun LEE


METHOD OF DEPOSITING ATOMIC LAYER AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE (18176692)

Main Inventor

Hyunjun AHN


METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE, AND APPARATUS EMPLOYING THE SAME (18086380)

Main Inventor

Kyungwook HWANG


SUBSTRATE PROCESSING APPARATUS AND METHOD (18314983)

Main Inventor

Hyung Jun Choi


FAN-OUT TYPE SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME (18085859)

Main Inventor

Joonho JUN


SEMICONDUCTOR PACKAGE AND DISPLAY APPARATUS INCLUDING THE SAME (18125409)

Main Inventor

Narae Shin


SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME (18154261)

Main Inventor

Yeongbeom KO


SEMICONDUCTOR PACKAGE (18130197)

Main Inventor

Eunkyul Oh


SEMICONDUCTOR PACKAGE (18303380)

Main Inventor

Kwang-Chul CHOI


SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME (18322570)

Main Inventor

Hyunsu Hwang


SEMICONDUCTOR PACKAGE (18244462)

Main Inventor

GWANGJAE JEON


SEMICONDUCTOR PACKAGE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS (18165419)

Main Inventor

Hyeonjun Song


SEMICONDUCTOR PACKAGE (18135623)

Main Inventor

Kiwon Baek


SEMICONDUCTOR PACKAGE (18142876)

Main Inventor

SUNJAE KIM


INTEGRATED CIRCUIT DEVICES INCLUDING METALLIC SOURCE/DRAIN REGIONS (18056181)

Main Inventor

Byounghak Hong


MANUFACTURING METHOD OF IMAGE SENSOR PACKAGE (18141295)

Main Inventor

Sunjae Kim


IMAGE SENSORS AND METHODS OF MANUFACTURING THE SAME (18342376)

Main Inventor

Hoemin JEONG


IMAGE SENSOR AND METHOD OF FABRICATING THE SAME (18367683)

Main Inventor

Sang-Hoon KIM


IMAGE SENSOR AND ELECTRONIC APPARATUS INCLUDING THE IMAGE SENSOR (18210946)

Main Inventor

Junho LEE


IMAGE SENSOR (18466475)

Main Inventor

KYUNG HO LEE


CAPACITORS OF SEMICONDUCTOR DEVICE CAPABLE OF OPERATING IN HIGH FREQUENCY OPERATION ENVIRONMENT (18462909)

Main Inventor

Jaeho LEE


METHOD OF MANUFACTURING METAL NITRIDE FILM AND ELECTRONIC DEVICE INCLUDING METAL NITRIDE FILM (18465439)

Main Inventor

Jeonggyu SONG


INTEGRATED CIRCUIT SEMICONDUCTOR DEVICE (18214861)

Main Inventor

Sungmin KIM


INTEGRATED CIRCUIT DEVICE (18088890)

Main Inventor

GYEOM KIM


SEMICONDUCTOR DEVICES (18110950)

Main Inventor

Da Hye Kim


SEMICONDUCTOR DEVICES (18195074)

Main Inventor

Kanghun Moon


METHOD OF MANUFACTURING MICRO-LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE SAME (18214808)

Main Inventor

Dongho KIM


SEMICONDUCTOR LIGHT EMITTING DEVICE (18213608)

Main Inventor

Mingu Ko


DISPLAY APPARATUS (18195534)

Main Inventor

Hyukjun JANG


SOLID-STATE ELECTROLYTE MATERIAL AND SOLID-STATE BATTERY UTILIZING THE SAME (18149635)

Main Inventor

Gabin YOON


ANTENNA AND ELECTRONIC DEVICE COMPRISING SAME (18244039)

Main Inventor

Youngjung KIM


ARRANGEMENT STRUCTURE FOR COMMUNICATION DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME (18464971)

Main Inventor

Jong Hyuck LEE


ELECTRONIC DEVICE INCLUDING BATTERY PACK, AND OPERATION METHOD OF ELECTRONIC DEVICE (18464671)

Main Inventor

Chanjung BAE


ELECTRONIC DEVICE METHOD FOR CONTROLLING CHARGING CURRENT FOR MULTIPLE BATTERIES BASED ON SENSING RESISTORS (18310111)

Main Inventor

Jinyoung JANG


ELECTRONIC DEVICE FOR WIRELESSLY RECEIVING POWER AND METHOD OF OPERATING THE SAME (18343511)

Main Inventor

Kyunghwan LEE


ELECTRONIC APPARATUS AND CONTROL METHOD THEREOF (18244061)

Main Inventor

Shinho KANG


ELECTRONIC DEVICE COMPRISING BOOST CIRCUIT, AND METHOD FOR CONTROLLING SAME ELECTRONIC DEVICE (18242356)

Main Inventor

Hangseok CHOI


CLOCK DATA RECOVERY CIRCUITS AND ELECTRONIC SYSTEMS THAT SUPPORT DATA-BASED CLOCK RECOVERY (18308754)

Main Inventor

Dongho Choi


MACHINE-LEARNING ERROR-CORRECTING CODE CONTROLLER (18362137)

Main Inventor

Ariel DOUBCHAK


APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM (18460244)

Main Inventor

Seho MYUNG


ELECTRONIC DEVICE AND METHOD FOR DIGITAL PREDISTORTION IN WIRELESS COMMUNICATION SYSTEM (18122755)

Main Inventor

Gilwoong KO


METHOD AND DEVICE FOR PERFORMING IMPROVED BEAM TRACKING IN NEXT-GENERATION WIRELESS COMMUNICATION SYSTEM (18254411)

Main Inventor

Sangho LEE


METHOD AND APPARATUS FOR PERFORMING COMMUNICATION IN WIRELESS COMMUNICATION SYSTEM (18334835)

Main Inventor

Wonjun KIM


METHOD AND APPARATUS FOR COMPRESSION-BASED CSI REPORTING (18464005)

Main Inventor

Md. Saifur Rahman


SYSTEM AND METHOD FOR FLIGHT MANAGEMENT OF A FLEET OF UNMANNED AERIAL VEHICLES (18325415)

Main Inventor

Prashant TRIPATHI


METHOD AND APPARATUS FOR PACKET TRANSMISSION AT SURVIVAL TIME STATE IN A WIRELESS COMMUNICATION SYSTEM (18341525)

Main Inventor

Sangkyu BAEK


TIMER OPERATING METHOD AND DEVICE ACCORDING TO HARQ ACTIVATION (18038363)

Main Inventor

Sangkyu BAEK


RESET SYNCHRONIZING CIRCUIT AND GLITCHLESS CLOCK BUFFER CIRCUIT FOR PREVENTING START-UP FAILURE, AND IQ DIVIDER CIRCUIT (18243442)

Main Inventor

Juyun LEE


NON-UNIFORM CONSTELLATIONS (18201897)

Main Inventor

Belkacem MOUHOUCHE


STORAGE DEVICES, METHODS OF OPERATING STORAGE DEVICES, AND STREAMING SYSTEMS INCLUDING STORAGE DEVICES (18314341)

Main Inventor

Sang-Hwa Jin


ELECTRONIC DEVICE AND METHOD FOR EXCHANGING A MESSAGE INCLUDING MEDIA CONTENT (18188461)

Main Inventor

Jibin AN


METHOD AND ELECTRONIC DEVICE FOR HANDLING SECURE VIRTUAL EVENT IN VIRTUAL ENVIRONMENT (18342500)

Main Inventor

Vishwanath Pethri KAMATH


ELECTRONIC DEVICE AND OPERATING METHOD OF A DECODER (18244107)

Main Inventor

Yong-Yun PARK


WEARABLE ELECTRONIC DEVICE AND OPTICAL FILM APPLIED THERETO (18244054)

Main Inventor

Jeahyuck LEE


ELECTRONIC DEVICE COMPRISING SPEAKER STRUCTURE (18244084)

Main Inventor

Jeeyoun KO


PORTABLE TERMINAL HAVING SPEAKER AND ACOUSTIC OUTPUT PATH FOR SPEAKER (18460209)

Main Inventor

Sungsoo JUN


AUDIO DATA PROCESSING METHOD AND ELECTRONIC DEVICE SUPPORTING SAME (18466318)

Main Inventor

Junseok PARK


METHOD AND APPARATUS FOR PERFORMING DIRECT COMMUNICATION WITH AT LEAST ONE OTHER USER EQUIPMENT (18461048)

Main Inventor

Yun-Sun BAEK


ELECTRONIC DEVICE AND OFFLINE DEVICE REGISTRATION METHOD (18230967)

Main Inventor

Taegu KIM


METHOD FOR REQUESTING AUTHENTICATION BETWEEN TERMINAL AND 3RD PARTY SERVER IN WIRELESS COMMUNICATION SYSTEM, TERMINAL THEREFOR, AND NETWORK SLICE INSTANCE MANAGEMENT DEVICE (18462833)

Main Inventor

Kisuk KWEON


METHOD AND APPARATUS FOR ENHANCED MULTI-LINK MULTI RADIO (EMLMR) OPERATION (18335011)

Main Inventor

Vishnu Vardhan Ratnam


METHOD AND APPARATUS OF SHARING INFORMATION RELATED TO STATUS (18462065)

Main Inventor

Jaesik YOON


METHOD AND PLMN FOR CONTROLLING DISASTER AREA FOR DISASTER ROAMING SERVICE IN WIRELESS NETWORK (18251274)

Main Inventor

Aman AGARWAL


APPARATUS AND METHOD FOR MEASUREMENT IN WIRELESS COMMUNICATION SYSTEM (18460435)

Main Inventor

Sangbum KIM


METHOD FOR AUTHENTICATING ACCESS LAYER ON BASIS OF PUBLIC KEY INFRASTRUCTURE IN CONSIDERATION OF HANDOVER IN NEXT-GENERATION WIRELESS COMMUNICATION SYSTEM (18035357)

Main Inventor

Donghyun JE


METHOD AND APPARATUS FOR MEASUREMENTS FOR UE MOBILITY BETWEEN NTN AND TN (18336812)

Main Inventor

Kyeongin Jeong


METHOD AND APPARATUS FOR HANDLING CELL SELECTION AND RE-SELECTION IN MR-DC SYSTEM (18459161)

Main Inventor

Alok Kumar JANGID


ELECTRONIC DEVICE FOR SELECTING CELL, AND OPERATION METHOD THEREFOR (18244019)

Main Inventor

Kyoungho LEE


FLEXIBLE RESTRICTED TARGET WAKE TIME OPERATION (18339916)

Main Inventor

Rubayet Shafin


METHOD AND APPARATUS OF INITIAL ACCESS IN NEXT GENERATION CELLULAR NETWORKS (18464713)

Main Inventor

Peng XUE


METHOD AND APPARATUS FOR SIDELINK POSITIONING IN WIRELESS COMMUNICATION SYSTEM (18340372)

Main Inventor

Cheolkyu SHIN


METHODS FOR RESUMING CELL SERVICE, NON-TRANSITORY COMPUTER READABLE STORAGE MEDIA FOR PERFORMING THE SAME, AND TERMINALS CAPABLE OF RESUMING CELL SERVICE (17881212)

Main Inventor

Weiqiang JIANG


DEVICE AND METHODS FOR MANAGING CHANNEL ALLOCATION IN CBRS (18238198)

Main Inventor

Ritik Prasad MATHUR


DEVICE AND METHOD FOR OPERATING DUAL CONNECTIVITY STRUCTURE IN WIRELESS COMMUNICATION SYSTEM (18462835)

Main Inventor

Yongjae MA


METHOD AND APPARATUS FOR TRANSMISSION AND RECEPTION OF SIDELINK INFORMATION IN UNLICENSED BAND (18338977)

Main Inventor

Sungjin PARK


METHOD AND APPARATUS FOR DATA TRANSMISSION OF TERMINAL IN WIRELESS COMMUNICATION SYSTEM (18464924)

Main Inventor

Jaehyuk Jang


CONTROL CHANNEL TRANSMITTING AND RECEIVING METHOD AND APPARATUS IN WIRELESS COMMUNICATION SYSTEM (18452188)

Main Inventor

Sungjin PARK


METHOD AND DEVICE FOR PROVIDING DIFFERENT SERVICES IN MOBILE COMMUNICATION SYSTEM (18465002)

Main Inventor

Sungnam Hong


METHOD AND DEVICE FOR SSB TRANSMISSION/RECEPTION IN WIRELESS COMMUNICATION SYSTEM (18039451)

Main Inventor

Hanjin KIM


METHODS AND PROCEDURE FOR NSTR START TIME SYNCHRONIZATION (18339161)

Main Inventor

Peshal Nayak


USER EQUIPMENT AND CALL RECOVERY METHOD EXECUTED BY THE SAME (18084061)

Main Inventor

Jianhua LIN


METHOD AND DEVICE FOR RE-ESTABLISHING PDCP IN WIRELESS COMMUNICATION SYSTEM (18460455)

Main Inventor

Seungri JIN


ELECTRONIC DEVICE COMPRISING WATERPROOF STRUCTURE AND MANUFACTURING METHOD THEREFOR (18243999)

Main Inventor

Gyeongtae KIM


ELECTRONIC DEVICE INCLUDING HOUSING, AND METHOD FOR MANUFACTURING HOUSING (18216530)

Main Inventor

Byungseon HWANG


FOLDABLE ELECTRONIC DEVICE COMPRISING HEAT-DISSIPATING STRUCTURE (18039656)

Main Inventor

Jaeyoung HUH


METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18213310)

Main Inventor

Eunjung Kim


SEMICONDUCTOR DEVICE (18133964)

Main Inventor

Jeesun Lee


SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18109442)

Main Inventor

Kiseok LEE


SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME (18149800)

Main Inventor

Jonghyeok KIM


SEMICONDUCTOR DEVICES (18192329)

Main Inventor

Jongmin KIM


SEMICONDUCTOR DEVICES (18464668)

Main Inventor

Youngwoo Kim


SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME (18190876)

Main Inventor

Donghoon KWON


SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME (18202111)

Main Inventor

Seulji LEE


SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME (18336497)

Main Inventor

Seokcheon BAEK


THREE-DIMENSIONAL (3D) SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME (18171858)

Main Inventor

Jeon Il LEE


STACK-TYPE SEMICONDUCTOR PACKAGE (18165412)

Main Inventor

KYUNG DON MUN


THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND ELECTRONIC SYSTEMS INCLUDING THE SAME (18180366)

Main Inventor

Jiwon Kim


INTEGRATED CIRCUIT DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME (18337180)

Main Inventor

Seokcheon Baek


HETEROCYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME (18242050)

Main Inventor

Eunsuk Kwon

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