18196703. SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Jongcheol Kim of Suwon-si (KR)
Hyongryol Hwang of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18196703 titled 'SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device that includes a memory cell array, a row hammer management circuit, and a column decoder.
- The row hammer management circuit counts the number of accesses based on an active command and performs a read-update-write operation to update the count data in the target memory cell row.
- The column decoder accesses a memory cell using a bit-line and stores data in the memory cell using a voltage. It can also perform an internal write operation to store count data in the memory cell using a higher voltage during a shorter time interval.
Potential applications of this technology:
- This semiconductor memory device can be used in various electronic devices such as computers, smartphones, and tablets.
- It can be utilized in data centers and server farms to improve memory performance and reliability.
Problems solved by this technology:
- Row hammer is a phenomenon where repeated accesses to a memory cell row can cause bit flips in neighboring cells. The row hammer management circuit in this device helps mitigate this issue by performing read-update-write operations.
- The internal write operation with a higher voltage and shorter time interval helps improve the efficiency of storing count data in memory cells.
Benefits of this technology:
- The row hammer management circuit helps prevent data corruption and improve the reliability of the memory device.
- The internal write operation with a higher voltage and shorter time interval reduces the time required for storing count data, enhancing the overall performance of the memory device.
Original Abstract Submitted
A semiconductor memory device, including a memory cell array; a row hammer management circuit configured to: count a number of accesses based on an active command, and based on a first command applied after the active command, perform an internal read-update-write operation to read the count data from the count cells of a target memory cell row, and to write updated count data in the count cells of the target memory cell row; and a column decoder configured to: access a first memory cell using a first bit-line; and store data in the first memory cell using a first voltage, or perform an internal write operation to store the count data in the first memory cell using a second voltage greater than the first voltage during an internal write time interval smaller than a reference write time interval.
