18213310. METHOD OF FABRICATING SEMICONDUCTOR DEVICE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
METHOD OF FABRICATING SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
METHOD OF FABRICATING SEMICONDUCTOR DEVICE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18213310 titled 'METHOD OF FABRICATING SEMICONDUCTOR DEVICE
Simplified Explanation
The patent application describes a method of manufacturing a semiconductor device. Here are the key points:
- The method involves forming a lower structure that includes a cell array region and an extension region. The cell array region has a first impurity region, a second impurity region, and word lines extending in a first direction. The extension region includes an insulating layer.
- A preliminary bit line structure is formed on the lower structure.
- A mask layer is formed on the preliminary bit line structure and the lower structure.
- Spacer patterns are formed on the mask layer, extending in a second direction that intersects the first direction.
- Material layers are formed on the side surfaces of the spacer patterns, on the extension region.
- Mask patterns are formed by patterning the mask layer using the spacer patterns and material layers as a first etching mask.
- Bit line structures are formed by patterning the preliminary bit line structure using the mask patterns as a second etching mask.
- Each bit line structure includes a first portion formed on the cell array region and a second portion formed on the extension region. The first portion is narrower than the second portion.
Potential applications of this technology:
- Manufacturing of semiconductor devices, such as memory chips or microprocessors.
Problems solved by this technology:
- Provides a method for manufacturing semiconductor devices with improved bit line structures.
- Allows for the formation of bit line structures that have different widths in different regions of the device.
Benefits of this technology:
- Enables the production of semiconductor devices with enhanced performance and functionality.
- Provides a more efficient and precise method for manufacturing bit line structures.
- Allows for the optimization of bit line widths in different regions of the device, improving overall device performance.
Original Abstract Submitted
A method of manufacturing a semiconductor device is provided. The method includes: forming a lower structure including a cell array region and an extension region, the cell array region including a first impurity region, a second impurity region and word lines extending in a first direction, and the extension region including an insulating layer; forming a preliminary bit line structure on the lower structure; forming a mask layer on the preliminary bit line structure and the lower structure; forming spacer patterns extending in a second direction, intersecting the first direction, on the mask layer; forming material layers on side surfaces of the spacer patterns, on the extension region; forming mask patterns by patterning the mask layer using the spacer patterns and the material layers as a first etching mask; and forming bit line structures by patterning the preliminary bit line structure using the mask patterns as a second etching mask. Each of the bit line structures includes a first portion formed on the cell array region and a second portion formed on the extension region, and the first portion is narrower than the second portion.
