18303380. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
Kwang-Chul Choi of Suwon-si (KR)
Sang Hyun Lee of Suwon-si (KR)
Un-Byoung Kang of Suwon-si (KR)
Jung Hoon Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18303380 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package that includes a package substrate, a semiconductor chip, a capacitor, connecting terminals, and a metal line within a trench in the package substrate. The metal line is positioned between the capacitor and the connecting terminals, and it is spaced apart from the capacitor by a certain distance.
- The semiconductor package includes a package substrate with a first and second side.
- A semiconductor chip is located on the first side of the package substrate.
- A capacitor is positioned on the second side of the package substrate.
- The second side of the package substrate also has a plurality of connecting terminals.
- A metal line is present within a trench in the package substrate.
- The trench extends in a first direction, and the metal line is situated between the capacitor and the connecting terminals.
- The metal line is spaced apart from the capacitor in a second direction, which is perpendicular to the first direction.
- The distance between the metal line and the capacitor is between 100 μm and 1000 μm.
Potential applications of this technology:
- Semiconductor packaging for electronic devices
- Integrated circuits and microchips
- Consumer electronics
- Automotive electronics
- Telecommunications equipment
Problems solved by this technology:
- Efficient placement of components in a semiconductor package
- Minimizing interference between the metal line and the capacitor
- Optimizing the performance and reliability of the semiconductor package
Benefits of this technology:
- Improved functionality and performance of electronic devices
- Enhanced reliability and durability of semiconductor packages
- Efficient use of space within the package substrate
- Reduced interference and noise in the circuitry
Original Abstract Submitted
A semiconductor package includes a package substrate having a first side and an opposite second side, a semiconductor chip on the first side of the package substrate, a capacitor on the second side of the package substrate, a plurality of connecting terminals on the second side of the package substrate, and a metal line within a trench in the package substrate. The trench extends in a first direction, and the metal line is between the capacitor and the plurality of connecting terminals. The metal line is spaced apart from the capacitor in a second direction that is transverse to the first direction, and a distance between the metal line and the capacitor is 100 μm or more and 1000 μm or less.
