18130197. SEMICONDUCTOR PACKAGE simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE
Organization Name
Inventor(s)
SEMICONDUCTOR PACKAGE - A simplified explanation of the abstract
This abstract first appeared for US patent application 18130197 titled 'SEMICONDUCTOR PACKAGE
Simplified Explanation
The patent application describes a semiconductor package design that includes a package substrate, a semiconductor chip, and a non-conductive film layer.
- The package substrate has a redistribution layer with first and second pads, and a solder mask layer with an opening exposing the first pads and a portion of the second pads.
- The semiconductor chip is placed on the package substrate and has connection pads that are electrically connected to the redistribution layer.
- Connection bumps connect the connection pads to the first pads, and a non-conductive film layer is placed between the semiconductor chip and the package substrate.
- The second pads are positioned on both sides of the first pads in at least one direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in that direction.
Potential applications of this technology:
- Semiconductor packaging industry
- Electronics manufacturing
Problems solved by this technology:
- Improved electrical connections between the semiconductor chip and the package substrate
- Enhanced protection of the connection pads and redistribution layer
Benefits of this technology:
- Increased reliability and performance of semiconductor packages
- Simplified manufacturing process
- Enhanced protection against electrical shorts and other damage
Original Abstract Submitted
A semiconductor package includes a package substrate including a redistribution layer including first pads and second pads on an upper surface thereof and a solder mask layer having an opening exposing the first pads entirely and exposing at least portion of each of the second pads, a semiconductor chip on the upper surface of the package substrate and including connection pads electrically connected to the redistribution layer, connection bumps below the semiconductor chip and connecting the connection pads to the first pads, and a non-conductive film layer between the semiconductor chip and the package substrate, wherein the second pads are respectively disposed on both sides of the first pads at least in a first direction, and the connection bumps are spaced apart from the second pads and the solder mask layer in the first direction.
