18189756. MEMORY CHIP AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
MEMORY CHIP AND MEMORY SYSTEM INCLUDING THE SAME
Organization Name
Inventor(s)
Kwangsook Noh of Suwon-si (KR)
MEMORY CHIP AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18189756 titled 'MEMORY CHIP AND MEMORY SYSTEM INCLUDING THE SAME
Simplified Explanation
The abstract describes a memory chip that consists of multiple storage blocks, each containing multiple memory cells. The chip also includes a logic circuit that controls the storage blocks. The logic circuit has an input/output pad for data input and output to the storage blocks.
- The logic circuit allocates block address codes with a bit inversion relationship, meaning they are the opposite of each other.
- It outputs a mode selection signal based on external control.
- In the first addressing mode, it outputs an external address code.
- In the second addressing mode, it outputs an address code that is the bit inversion of the external address code.
- It selects a storage block to be controlled based on the access command.
Potential applications of this technology:
- Memory chips used in various electronic devices such as computers, smartphones, and tablets.
- Data storage systems that require efficient memory management.
Problems solved by this technology:
- Efficient allocation and control of storage blocks in a memory chip.
- Simplified addressing modes for accessing memory cells.
Benefits of this technology:
- Improved memory chip performance and efficiency.
- Simplified memory management for system designers.
- Enhanced data storage and retrieval capabilities.
Original Abstract Submitted
A memory chip includes a plurality of storage blocks respectively including a plurality of memory cells; and a logic circuit configured to control the plurality of storage blocks, wherein the logic circuit includes an input/output pad configured to input data to the plurality of storage blocks and output data to the plurality of storage blocks; wherein the logic circuit is further configured to allocate block address codes having a bit inversion relationship with each other, output a mode selection signal in response to external control, output an external address code in response to the mode selection signal indicating a first addressing mode, and output an address code having a bit inversion relationship with regard to the external address code in response to the mode selection signal indicating a second addressing mode, and select a storage block to be controlled by the access command from among the plurality of storage blocks.
