18136915. SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Organization Name
Inventor(s)
Jongcheol Kim of Suwon-si (KR)
SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18136915 titled 'SEMICONDUCTOR MEMORY DEVICES AND MEMORY SYSTEMS INCLUDING THE SAME
Simplified Explanation
The patent application describes a semiconductor memory device that includes a memory cell array, a row hammer management circuit, and a refresh control circuit.
- The row hammer management circuit automatically stores random count data in count cells of each memory cell row during the power-up sequence of the device.
- The circuit determines counted values by counting the number of times each memory cell row is accessed in response to an active command from an external memory controller.
- The counted values are then stored in the count cells of each memory cell row as count data.
- The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more memory cell rows that are physically adjacent to the memory cell row corresponding to the hammer address.
Potential applications of this technology:
- Semiconductor memory devices used in various electronic devices such as computers, smartphones, and tablets.
- Memory-intensive applications that require efficient memory management and refresh operations.
Problems solved by this technology:
- Row hammer is a phenomenon where repeated accessing of memory cells in a specific row can cause bit flips in adjacent rows, leading to data corruption and security vulnerabilities.
- The row hammer management circuit and refresh control circuit help mitigate the effects of row hammer by automatically storing count data and performing refresh operations on adjacent memory cell rows.
Benefits of this technology:
- Improved reliability and data integrity of semiconductor memory devices.
- Enhanced security by reducing the risk of data corruption and potential exploits related to row hammer attacks.
- Efficient memory management and refresh operations, leading to better overall performance of electronic devices.
Original Abstract Submitted
A semiconductor memory device includes a memory cell array, a row hammer management circuit and a refresh control circuit. The row hammer management circuit automatically stores random count data in count cells of each of a plurality of memory cell rows during a power-up sequence of the semiconductor memory device and determines counted values by counting a number of times of access associated with each of the plurality of memory cell rows in response to an active command from an external memory controller and stores the counted values in the count cells of each of the plurality of memory cell rows as count data. The refresh control circuit receives a hammer address and performs a hammer refresh operation on one or more of the plurality of memory cell rows that are physically adjacent to a memory cell row that corresponds to the hammer address.
