18308754. CLOCK DATA RECOVERY CIRCUITS AND ELECTRONIC SYSTEMS THAT SUPPORT DATA-BASED CLOCK RECOVERY simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
CLOCK DATA RECOVERY CIRCUITS AND ELECTRONIC SYSTEMS THAT SUPPORT DATA-BASED CLOCK RECOVERY
Organization Name
Inventor(s)
Kwanghee Choi of Suwon-si (KR)
CLOCK DATA RECOVERY CIRCUITS AND ELECTRONIC SYSTEMS THAT SUPPORT DATA-BASED CLOCK RECOVERY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18308754 titled 'CLOCK DATA RECOVERY CIRCUITS AND ELECTRONIC SYSTEMS THAT SUPPORT DATA-BASED CLOCK RECOVERY
Simplified Explanation
The clock data recovery circuit described in this patent application is designed to generate multiple clock signals with different phases based on a received clock signal. These clock signals are used to generate multiphase sampling clock signals for sampling a received data signal.
- The circuit includes a phase-locked loop (PLL) that generates clock signals with unequal phases.
- A phase interpolator is used to interpolate the phases of the clock signals during the generation of multiphase sampling clock signals.
- A sampling clock adjustment circuit is provided to generate data symbols by sampling the received data signal at specific time points determined by the multiphase sampling clock signals.
- The adjustment circuit detects two different data patterns, one with a transition point before a reference data symbol and another with a transition point after a reference data symbol.
- The circuit measures the signal levels of these data patterns at the respective sampling time points for the reference data symbols.
- Based on the comparison of the signal levels, the circuit adjusts the phases of the multiphase sampling clock signals.
Potential applications of this technology:
- High-speed data communication systems that require accurate clock recovery and sampling of data signals.
- Digital signal processing applications that involve precise timing and synchronization of data signals.
Problems solved by this technology:
- Clock recovery circuits often struggle to accurately sample data signals due to phase misalignment.
- Traditional clock recovery circuits may require complex algorithms or additional components to adjust the clock phases.
- This innovation provides a simplified and efficient solution for adjusting clock phases based on the detected data patterns.
Benefits of this technology:
- Improved accuracy in sampling data signals, leading to better overall system performance.
- Simplified design and implementation of clock recovery circuits.
- Reduced complexity and cost compared to traditional clock recovery methods.
Original Abstract Submitted
A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.
