Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 26th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 26th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to integrated chips, memory devices, interconnect structures, and manufacturing methods. These patents demonstrate TSMC's focus on developing innovative technologies for the semiconductor industry.

Summary of Recent Patents:

- Integrated Chip with Multiple Layers: TSMC has developed an integrated chip that includes multiple layers of conductive and dielectric materials. The chip features a data storage structure consisting of three dielectric layers with different bandgaps, providing enhanced performance and functionality.

- Memory Device with Shielding Element: TSMC has designed a memory device that includes a memory unit and a shielding element. The shielding element is placed on the memory unit to redirect any external magnetic field away from the memory element, ensuring reliable and stable operation.

- Interconnect Structure with Conductive Pad and Capping Layer: TSMC has developed an interconnect structure with two interconnect elements. The structure includes a conductive pad layer covered by a capping layer made of titanium nitride, providing improved conductivity and protection against oxidation.

- Integrated Chip with Fin Structure and Ferroelectric Memory Stack: TSMC has created an integrated chip with a fin structure extending vertically from a semiconductor substrate. The fin structure is covered by a ferroelectric memory stack, which extends laterally in a different direction. This design allows for efficient memory storage and retrieval.

- Memory Device with Stacking Structure and Conductive Pillars: TSMC has developed a memory device with multiple layers stacked on top of each other. The device includes a stacking structure made up of alternating isolation layers and word lines, as well as conductive pillars aligned perpendicular to the layers.

Notable Applications:

• Inline Tin Stream Monitor (ITSM) system for accurate measurement and estimation of tin levels in an in-line refill system.
• Automatic gain adjustor for a hybrid oscillator to overcome frequency limitations of hybrid phase lock loops (PLLs), allowing for precise frequency control.

These recent patents and applications demonstrate TSMC's commitment to advancing semiconductor technology and addressing key challenges in the industry. Through innovative designs and manufacturing methods, TSMC aims to enhance the performance, reliability, and efficiency of integrated chips and memory devices.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 26th, 2023

METHOD OF USING POLISHING PAD (18341421)

Main Inventor

ChunHung CHEN

Brief explanation

This abstract describes a method of using a polishing pad. The method involves applying a slurry to a specific location on the polishing pad and then rotating the pad. The slurry is spread across different regions of the pad at different rates. The first region, which has a set of grooves, is spread at a certain rate. The second region, which surrounds the first region and also has grooves, is spread at a different rate. Finally, the third region, which surrounds the second region and has its own set of grooves, is spread at a slower rate than the first two regions.

Abstract

A method of using a polishing pad includes applying a slurry to a first location on the polishing pad. The method further includes rotating the polishing pad. The method further includes spreading the slurry across a first region of the polishing pad at a first rate, wherein the first region includes a plurality of first grooves. The method further includes spreading the slurry across a second region, surrounding the first region of the polishing pad at a second rate different from the first rate, wherein the second region includes a plurality of second grooves. The method further includes spreading the slurry across a third region, surrounding the second region of the polishing pad at a third rate less than the first rate and the second rate, wherein the third region includes a plurality of third grooves.

INTEGRATED OPTICAL DEVICES AND METHODS OF FORMING THE SAME (17725558)

Main Inventor

Feng-Wei Kuo

Brief explanation

The abstract describes an integrated optical device that consists of a substrate, a waveguide structure, and a grating structure. The substrate has two adjacent regions - a waveguide region and a grating region. The waveguide structure is placed on the substrate in the waveguide region, while the grating structure is placed on the substrate in the grating region. The grating structure is made up of grating bars and grating intervals arranged alternately, and the widths of the grating bars vary.

Abstract

An integrated optical device includes a substrate, a waveguide structure and a grating structure. The substrate has a waveguide region and a grating region adjacent to each other. The waveguide structure is disposed on the substrate in the waveguide region. The grating structure is disposed on the substrate in the grating region. In some embodiments, the grating structure includes grating bars and grating intervals arranged alternately, and widths of the grating bars of the grating structure are varied.

METHOD OF FABRICATING AND SERVICING A PHOTOMASK (18210551)

Main Inventor

Chun-Fu YANG

Brief explanation

The abstract describes a method for removing contamination from a photomask using plasma processing. The contaminated photomask is placed in a plasma processing chamber and treated with either oxygen plasma or hydrogen plasma to remove the contamination from its surface.

Abstract

A method includes placing a photomask having a contamination on a surface thereof in a plasma processing chamber. The contaminated photomask is plasma processed in the plasma processing chamber to remove the contamination from the surface. The plasma includes oxygen plasma or hydrogen plasma.

PHOTORESIST COMPOSITION WITH NOVEL SOLVENT (17726036)

Main Inventor

An-Ren ZI

Brief explanation

The abstract describes a method for making a semiconductor device. It involves applying a layer of photoresist material onto a substrate, exposing it to a specific type of radiation called EUV, and then developing the exposed layer. The photoresist material used contains a mixture of solvents and a component that contains metal dissolved in the solvents. One of the solvents used is a primary alcohol.

Abstract

A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate, exposing the photoresist layer to an EUV radiation, and developing the exposed photoresist layer. The photoresist layer has a composition including a solvent mixture and a metal-containing component dissolved in the solvent mixture. The solvent mixture includes a first solvent comprising primary alcohol.

CHIP POWER CONSUMPTION ANALYZER AND ANALYZING METHOD THEREOF (17829376)

Main Inventor

Sin-Huei Li

Brief explanation

The abstract describes a chip power consumption analyzer and a method for analyzing power consumption in a circuit. The method involves receiving design information of the circuit and calculating the clock arriving times of various circuit cells based on this information. A base cell type is then determined based on the clock arriving times. The method establishes base demand current information for the base cell type and obtains demand current information for the other circuit cells. Finally, the method predicts the demand peak currents of bump current sources based on the demand current information and the position information of the circuit cells.

Abstract

Disclosed are a chip power consumption analyzer and an analyzation method thereof. The analyzation method includes the following. Design information of a circuit is received. A plurality of clock arriving times of a plurality of circuit cells in the circuit are calculated based on the design information, and a base cell type is set among a plurality of cell types according to the clock arriving times. Base demand current information of the base cell type is established, and a plurality of demand current information of the circuit cells is obtained. A plurality of demand peak currents of a plurality of bump current sources are predicted according to the demand current information and a plurality of position information of the circuit cells.

METHOD FOR INTRA-CELL-REPURPOSING DUMMY TRANSISTORS AND SEMICONDUCTOR DEVICE HAVING REPURPOSED FORMERLY DUMMY TRANSISTORS (17743374)

Main Inventor

Yiyun HUANG

Brief explanation

The abstract describes a method for creating a cell in a layout diagram. The method involves selecting a cell from a library of standard cells, which are components that make up an active circuit. Within the selected cell, there is a dummy device that is not connected to the active circuit. The method involves connecting this dummy device to a specific node within the active circuit.

Abstract

In some embodiments, a method of generating a cell in a layout diagram includes: selecting a cell from a library of standard cells, components of the cell defining an active circuit; identifying a dummy device within the cell that is disconnected from the active circuit within the cell; and connecting the dummy device to a target node of the active circuit.

INTEGRATED CIRCUIT, SYSTEM AND METHOD OF FORMING THE SAME (18333259)

Main Inventor

Shih-Wei PENG

Brief explanation

This abstract describes an integrated circuit that consists of various components. It mentions a first power rail, which is located on the back-side of a substrate and supplies a specific voltage. There is also a first signal line on the back-side of the substrate, separate from the first power rail. The circuit includes a first transistor with an active region on the front-side of the substrate, which overlaps with the first power rail and is connected to it. Additionally, there is a second transistor with a separate active region on the front-side of the substrate, which is overlapped by the first signal line. This second active region is designed to receive the first supply voltage from the first power rail through the first active region of the first transistor.

Abstract

An integrated circuit includes a first power rail, a first signal line, a first transistor and a second transistor. The first power rail is on a back-side of a substrate and is configured to supply a first supply voltage. The first signal line is on the back-side of the substrate and is separated from the first power rail. The first transistor has a first active region is in a front-side of the substrate. The first active region is overlapped by the first power rail and is electrically coupled to the first power rail. The second transistor has a second active region that is in the front-side of the substrate. The second active region is separated from the first active region, is overlapped by the first signal line, and is configured to receive the first supply voltage of the first power rail through the first active region of the first transistor.

CAPTURE IR DROP ANALYZER AND ANALYZING METHOD THEREOF (17844083)

Main Inventor

Chen-Yuan Kao

Brief explanation

The abstract describes a capture IR drop analyzer and a method for analyzing it. The analyzer receives information about the circuit layout and package model of a circuit. It then analyzes different circuit blocks corresponding to bump current sources based on this information. It calculates critical circuit blocks based on the bump current sources and the current demand of each circuit block. Finally, it analyzes the clock tree architecture of the critical circuit blocks to obtain information for adjusting the design structure.

Abstract

A capture IR drop analyzer and an analyzing method thereof are provided. The capture IR drop analyzing method includes: receiving circuit layout information and package model information of a circuit; analyzing a plurality of circuit blocks respectively corresponding to a plurality of bump current sources according to the circuit layout information and the package model information; calculating at least one critical circuit block according to each of the bump current sources and a current demand value of each of the corresponding circuit blocks; and analyzing a clock tree architecture of the at least one critical circuit block to obtain design structure adjustment information.

STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME (18333392)

Main Inventor

Chih-Yu LIN

Brief explanation

The abstract describes a type of memory called static random access memory (SRAM) that has two memory cell arrays. It also includes various components such as word lines, bit lines, driver circuits, and supplementary driver circuits. During a write operation, the first supplementary driver circuit pulls the voltage of a signal on the bit line or its complement to a specific level. The second supplementary driver circuit senses the voltage of the signal and includes a pass-gate transistor that is connected to a reference voltage supply and a first node.

Abstract

A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.

DUO-LEVEL WORD LINE DRIVER (18345071)

Main Inventor

Po-Hao Lee

Brief explanation

The abstract describes a circuit that consists of two transistors connected to each other in a specific way. The first transistor's source and the second transistor's source are connected to a power supply. The gate of the first transistor is connected to the drain of the second transistor at a first node, and the gate of the second transistor is connected to the drain of the first transistor at a second node.

This circuit is designed to provide different levels of voltage to a memory cell. It can directly connect the power supply, which is set at a first level, to the memory cell through the second transistor and a third transistor, in order to provide a first level of voltage to the memory cell. Similarly, it can directly connect the power supply, which is set at a second level, to the memory cell through the second transistor and the third transistor, in order to provide a second level of voltage to the memory cell.

In summary, this circuit allows for the provision of different voltage levels to a memory cell by directly connecting the power supply to the memory cell through specific transistors.

Abstract

A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.

MEMORY DEVICE AND OPERATING METHOD OF THE SAME (18345530)

Main Inventor

Gu-Huan LI

Brief explanation

This abstract describes a memory device that consists of two bit cells. The first bit cell has a memory cell connected to a word line, while the second bit cell has a memory cell connected to a different word line. Both memory cells are also connected to a control line and a bit line through two nodes. The second bit cell also includes a protection array connected to its memory cell at one of the nodes and to a third word line. When the first and second bit cells are operating in different modes, the protection array generates an adjust voltage to one of the nodes based on the voltage level of the third word line while the first bit cell is being programmed.

Abstract

A memory device is provided, including a first bit cell including a first memory cell coupled to a first word line and a second bit cell including a second memory cell coupled to a second word line. The first and second memory cells are coupled to a first control line and further coupled to a first bit line through first and second nodes. The second bit cell further includes a first protection array coupled to the second memory cell at the second node coupled to the first bit line and further coupled to a third word line. When the first and second bit cells operate in different operational types, the first protection array is configured to generate an adjust voltage to the second node according to a voltage level of the third word line while the first bit cell is programmed.

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (17660169)

Main Inventor

Yi Chen HO

Brief explanation

The abstract describes techniques and apparatuses for preventing an injector nozzle from colliding with the interior wall of a thin-film furnace. This is achieved by using a fixture that is attached to the injector nozzle and can be adjusted to maintain a gap between the nozzle and the wall. This prevents any collision that could dislodge particles and contaminate semiconductor products made in the furnace.

Abstract

Some implementations described herein provide techniques and apparatuses for overcoming forces that may deflect an injector nozzle into an interior wall of a thin-film furnace. The implementations include a fixture that is coupled to the injector nozzle. The fixture is configurable to lock to a selected property of the injector nozzle to maintain, between a portion of the injector nozzle and the interior wall, a gap. In this way, the portion of the injector nozzle is prevented from colliding with the interior wall and dislodging particulates that may contaminate semiconductor product fabricated using the thin-film furnace.

SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (17660249)

Main Inventor

Liang Yu CHEN

Brief explanation

This abstract describes techniques and apparatuses for improving the uniformity of gas flow in an etch tool used in semiconductor manufacturing. The etch tool includes an exhaust port at the bottom center of the chamber and a flow-control subsystem consisting of an impeller and a thermal component. By adjusting the rotational velocity of the impeller and the amount of heat transferred from the thermal component, the flow of gas across the semiconductor substrate can be made more uniform. This leads to an increase in the uniformity of the etching rate and a decrease in contamination defects caused by particulate clustering. Ultimately, these improvements result in a higher yield of semiconductor products produced using the etch tool.

Abstract

Some implementations described herein provide techniques and apparatuses for improving a uniformity of a flow of a gas across a semiconductor substrate in an etch tool. The etch tool includes an exhaust port located at a bottom center of a chamber of the etch tool. The etch tool further includes a flow-control subsystem that includes an impeller and a thermal component. As a result of the flow-control subsystem varying a rotational velocity of the impeller, and/or an amount of heat transferred from the thermal component, the uniformity of the flow of the gas across the semiconductor substrate may be improved. In this way, a uniformity of an etching rate may be increased and contamination defects due to a clustering of particulates may be decreased, resulting in an increase in a yield of semiconductor product fabricated using the etch tool.

SPIN ON CARBON COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18216468)

Main Inventor

Jing Hong HUANG

Brief explanation

The abstract describes a composition that includes a carbon backbone polymer, a first crosslinker, and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature between 100°C and 170°C, while the second crosslinker fully crosslinks the carbon backbone polymer at a temperature between 180°C and 300°C. The first crosslinker is chosen from a group of compounds that have the structure A-(OR) or A-(NR).

Abstract

A composition, comprising: a carbon backbone polymer; a first crosslinker; and a second crosslinker. The first crosslinker partially crosslinks the carbon backbone polymer at a temperature ranging from 100° C. to 170° C., and the second crosslinker crosslinks the carbon backbone polymer at a temperature ranging from 180 20  C. to 300° C. The first crosslinker is one or more selected from the group consisting of A-(OR), A-(NR),

METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURE (17879595)

Main Inventor

Shahaji B. MORE

Brief explanation

The abstract describes a method for creating a semiconductor device structure. It involves several steps, including forming a first layer of semiconductor material on a substrate in a processing chamber. After that, a purge process is performed by introducing a gas containing chlorine into the chamber. Then, a second layer of semiconductor material is formed on top of the first layer. This results in the formation of an interface region between the two layers.

Abstract

A method for forming a semiconductor device structure is described. The method includes forming a first semiconductor layer over a substrate in a processing chamber and performing a purge process. The purge process includes flowing a chlorine-containing gas into the processing chamber. The method further includes forming a second semiconductor layer over the first semiconductor layer, and an interface region is formed between the first and second semiconductor layers.

SEMICONDUCTOR DEVICE WITH T-SHAPED ACTIVE REGION AND METHODS OF FORMING SAME (17742272)

Main Inventor

Huaixin XIAN

Brief explanation

This abstract describes a semiconductor device that consists of a cell region with active regions. These active regions contain components of transistors and extend in a specific direction. Most of the active regions are rectangular in shape. However, there is one active region that has a T-shape, with a stem extending in a different direction and two arms extending from the same end of the stem. Additionally, there are two majorities of active regions that are aligned at their ends, forming reference lines parallel to the boundaries of the cell region.

Abstract

A semiconductor device includes: a cell region including active regions that extend in a first direction and have components of corresponding transistors formed therein; a first majority of the active regions being rectangular; a first one of the active regions having a T-shape including a stem that extends in a second direction perpendicular to the first direction, and, relative to the first direction, first and second arms that extend from a same end of the stem and away from each other; and, relative to the first direction, a second majority of the active regions having aligned first ends defining a first reference line proximate and parallel to a first boundary of the cell region, and a third majority of the active regions having aligned second ends defining a second reference line proximate and parallel to a second boundary of the cell region.

Mechanism for FinFET Well Doping (18346622)

Main Inventor

Chun Hsiung Tsai

Brief explanation

This abstract describes a method for improving the performance of finFET devices by doping the well regions. The method involves depositing doped films before forming isolation structures, which helps maintain a low dopant concentration in the channel regions. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide using microwave annealing. This conversion process does not cause dopant diffusion. Additional well implants may be performed to create deep wells, and microwave annealing can also be used to fix any defects in the substrate and fins. Overall, this method enhances transistor performance in finFET devices.

Abstract

The embodiments of mechanisms for doping wells of finFET devices described in this disclosure utilize depositing doped films to dope well regions. The mechanisms enable maintaining low dopant concentration in the channel regions next to the doped well regions. As a result, transistor performance can be greatly improved. The mechanisms involve depositing doped films prior to forming isolation structures for transistors. The dopants in the doped films are used to dope the well regions near fins. The isolation structures are filled with a flowable dielectric material, which is converted to silicon oxide with the usage of microwave anneal. The microwave anneal enables conversion of the flowable dielectric material to silicon oxide without causing dopant diffusion. Additional well implants may be performed to form deep wells. Microwave anneal(s) may be used to anneal defects in the substrate and fins.

SEMICONDUCTOR DEVICE AND METHODS OF FORMATION (17660518)

Main Inventor

Ying-Yu LAI

Brief explanation

Multiple dry etching operations are used to create an opening for an interconnect structure in a semiconductor device. In between these dry etching operations, a wet cleaning operation is performed. This multi-step etch approach improves the removal of leftover materials, resulting in a higher quality interconnect structure. It also reduces the chances of under etching, leading to better semiconductor device yield and performance.

Abstract

Multiple dry etching operations are performed to form an opening for an interconnect structure, with a wet cleaning operation performed in between the dry etching operations. This multi-step etch approach increases the effectiveness of residual material removal, which increases the quality of the interconnect structure and reduces the likelihood of under etching, both of which increase semiconductor device yield and semiconductor device performance.

SEMICONDUCTOR DEVICE STRUCTURE (18347264)

Main Inventor

Chun-Hung LIAO

Brief explanation

This abstract describes the structure of a semiconductor device. It consists of a gate structure and a source/drain structure formed on a substrate. A contact structure is also present, along with a first cap layer formed over it. Additionally, there is a dielectric structure that extends from the top surface of the first cap layer into the contact structure. The dielectric structure separates the contact structure from the source/drain structure.

Abstract

A semiconductor device structure includes a gate structure formed over a substrate. The semiconductor device structure also includes a source/drain structure formed beside the gate structure. The semiconductor device structure further includes a contact structure formed over the source/drain structure. The semiconductor device structure also includes a first cap layer formed over the contact structure. The semiconductor device structure further includes a dielectric structure extending from a top surface of the first cap layer into the contact structure. The dielectric structure and the source/drain structure are separated by the contact structure.

FILM SCHEME TO REDUCE PLASMA-INDUCED DAMAGE (17856419)

Main Inventor

Chia-Wen Zhong

Brief explanation

The abstract describes an integrated chip structure that includes a substrate and various layers. The structure includes lower interconnects within a lower inter-level dielectric structure, and a plasma induced damage (PID) mitigation layer made of a porous metal structure. There is also an upper interconnect surrounded by an upper ILD structure, which extends from over the PID mitigation layer to the lower interconnects.

Abstract

The present disclosure relates to an integrated chip structure. The integrated chip structure includes a substrate. One or more lower interconnects are disposed within a lower inter-level dielectric (ILD) structure over the substrate. A plasma induced damage (PID) mitigation layer is disposed over the lower ILD structure. The PID mitigation layer has a porous structure including a metal. A first upper interconnect is laterally surrounded by an upper ILD structure over the PID mitigation layer. The first upper interconnect extends from over the PID mitigation layer to the one or more lower interconnects.

TESTING MODULE AND METHOD FOR USING THE SAME (17724928)

Main Inventor

Jen-Yuan CHANG

Brief explanation

This method involves the fabrication and testing of an integrated circuit on a wafer. The integrated circuit and a testing pattern are formed using the same process. A testing chip is connected to the testing pattern, and electrical properties of the pattern are detected to perform a testing process on the integrated circuit. Once testing is complete, an interconnection structure is formed over the integrated circuit, which includes conductive features that are connected to the circuit. Finally, the wafer is singulated into individual die through a process called singulation.

Abstract

A method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed by a same fabrication process; connecting a via of a testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; after the testing process is completed, forming an interconnection structure over the integrated circuit, in which the interconnection structure includes conductive features electrically connected to the integrated circuit; and after the interconnection structure is formed over the integrated circuit performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.

SEMICONDUCTOR STRUCTURE HAVING THROUGH SUBSTRATE VIA AND MANUFACTURING METHOD THEREOF (17727820)

Main Inventor

Wei-Ming Wang

Brief explanation

The abstract describes a semiconductor structure that includes several components. These components include a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate, a through substrate via (TSV), and a dielectric liner. 

The dielectric layer is a layer of material that acts as an insulator. The conductive pad is a small area within the dielectric layer that allows for electrical connections.

The semiconductor substrate is a material that serves as the foundation for the semiconductor structure. It has a via opening, which is a hole or opening in the substrate. This via opening has a notch, which is a small indentation or cut, near the dielectric layer.

The TSV is a vertical connection that extends from the via opening in the semiconductor substrate into the dielectric layer. It lands on the conductive pad, allowing for electrical connections.

The dielectric liner is a material that is placed in the via opening of the semiconductor substrate. It fills the notch, which helps to separate the TSV from the semiconductor substrate in a lateral direction.

The surface of the dielectric liner that faces the TSV is leveled with the inner sidewall of the dielectric layer that faces the TSV. This means that these two surfaces are made to be at the same height or level.

Overall, this semiconductor structure is designed to provide efficient electrical connections while also ensuring proper separation and insulation between different components.

Abstract

A semiconductor structure includes a dielectric layer, a conductive pad embedded in the dielectric layer, a semiconductor substrate disposed on the dielectric layer and including a via opening with a notch in proximity to the dielectric layer, a through substrate via (TSV) disposed in the via opening of the semiconductor substrate and extending into the dielectric layer to land on the conductive pad, and a dielectric liner disposed in the via opening of the semiconductor substrate and filling the notch to laterally separate the TSV from the semiconductor substrate. A surface of the dielectric liner facing the TSV is substantially leveled with an inner sidewall of the dielectric layer facing the TSV.

INTEGRATED CHIP HAVING A BACK-SIDE POWER RAIL (18341831)

Main Inventor

Shin-Yi Yang

Brief explanation

The abstract describes an integrated chip that includes a semiconductor device. The semiconductor device has a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The gate structure surrounds the stack of channel structures and is located between the first and second source/drain structures. A first conductive wire is positioned above the semiconductor device but is not in direct contact with it. The first conductive wire consists of multiple conductive layers. A first conductive contact connects the first conductive wire to the first source/drain structure by passing through a dielectric layer. The first conductive contact is located on the back-side of the first source/drain structure.

Abstract

The present disclosure relates to an integrated chip including a semiconductor device. The semiconductor device includes a first source/drain structure, a second source/drain structure, a stack of channel structures, and a gate structure. The stack of channel structures and the gate structure are between the first and second source/drain structures. The gate structure surrounds the stack of channel structures. A first conductive wire overlies and is spaced from the semiconductor device. The first conductive wire includes a first stack of conductive layers. A first conductive contact extends through a dielectric layer from the first conductive wire to the first source/drain structure. The first conductive contact is on a back-side of the first source/drain structure.

SEMICONDUCTOR DEVICE INCLUDING THROUGH VIA AND METHOD OF MAKING (17727504)

Main Inventor

Chih-Yu LAI

Brief explanation

This abstract describes a semiconductor device that consists of a substrate. On one side of the substrate, there is a conductive mesh, while on the other side, there is an active region. The conductive mesh is connected to the active region through a through via that goes through the substrate. Additionally, there is a contact structure on the second side of the substrate, which is directly connected to the active region and overlaps the top surface of the through via.

Abstract

A semiconductor device includes a substrate. The semiconductor device further includes a conductive mesh on a first side of the substrate. The semiconductor device further includes an active region on a second side of the substrate, wherein the first side of the substrate is opposite to the second side of the substrate. The semiconductor device further includes a through via electrically connected to the conductive mesh, wherein the through via extends through the substrate. The semiconductor device further includes a contact structure on the second side of the substrate, wherein the contact structure is electrically connected to the active region, the contact structure is in direct contact with the through via, and the contact structure overlaps a top surface of the through via in a top view.

PAD STRUCTURE FOR ENHANCED BONDABILITY (18340092)

Main Inventor

Ru-Ying Huang

Brief explanation

The abstract describes a pad with high strength and bondability. It explains that the pad is part of an integrated chip and is connected to a substrate through an interconnect structure. The interconnect structure consists of wires and vias that are stacked between the pad and the substrate. The abstract also mentions a conductive structure, such as a wire bond, that extends through the substrate to the pad. This arrangement allows the pad to be inset into a passivation layer of the interconnect structure, which helps absorb stress on the pad. The pad also contacts the wires and vias at a top wire level, which is thicker and more tolerant to stress compared to other wire levels.

Abstract

Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.

PACKAGE STRUCTURE (18336258)

Main Inventor

Po-Chen LAI

Brief explanation

This abstract describes a package structure for a semiconductor die. The structure includes a redistribution structure, bonding elements, and an underfill layer. The semiconductor die has a rectangular shape when viewed from above. The pitch of the bonding elements is defined as the sum of the diameter of the bonding elements and the spacing between them. The redistribution structure has a circular area that is completely covered by and in direct contact with the underfill layer. The center of this circular area is aligned with one corner of the rectangular shape of the semiconductor die. The diameter of this circular area is larger than twice the pitch of the bonding elements.

Abstract

A package structure is provided. The package structure includes a semiconductor die over a redistribution structure, bonding elements below the redistribution structure, and an underfill layer surrounding the bonding elements and the redistribution structure. The semiconductor die has a rectangular profile in a plan view. A pitch of the bonding elements is defined as the sum of a diameter of the bonding elements and a spacing between neighboring two of the bonding elements. A first circular area of the redistribution structure is entirely covered and in direct contact with the underfill layer. The center of the first circular area is aligned with a first corner of the rectangular profile of the semiconductor die. A diameter of the first circular area is greater than twice the pitch of the bonding elements.

CHIP PACKAGE STRUCTURE (18344039)

Main Inventor

Po-Chen LAI

Brief explanation

The abstract describes a chip package structure that includes a redistribution structure with multiple wiring layers. There is also a shield bump structure that is insulated from the wiring layers. The structure includes a first chip that is bonded to the redistribution structure and is insulated from the shield bump structure. The first chip partially overlaps the shield bump structure. Additionally, there is a second chip that is also bonded to the redistribution structure.

Abstract

A chip package structure is provided. The chip package structure includes a redistribution structure including a dielectric structure and a plurality of wiring layers in or over the dielectric structure. The chip package structure includes a shield bump structure over the redistribution structure and electrically insulated from the wiring layers. The chip package structure includes a first chip structure bonded to the redistribution structure. The first chip structure is electrically insulated from the shield bump structure, and the first chip structure partially overlaps the shield bump structure. The chip package structure includes a second chip structure bonded to the redistribution structure.

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18342752)

Main Inventor

Hsien-Wei Chen

Brief explanation

This abstract describes a semiconductor package that consists of two dies. The first die contains two coils of an inductor, which are positioned at different heights. The first coil is made of a certain metallic material, while the second coil is made of a different metallic material with a distinct composition. The second die is connected to the first die and includes a third coil of the inductor. The inductor spans from the first die to the second die.

Abstract

A semiconductor package includes a first die and a second die. The first die includes a first coil and a second coil of an inductor. The first coil and the second coil are located at different level heights. The first coil includes a first metallic material. The second coil includes a second metallic material. The first metallic material has a different composition from the second metallic material. The second die is bonded to the first die. The second die includes a third coil of the inductor. The inductor extends from the first die to the second die.

FLIP-CHIP BONDING APPARATUS AND METHOD OF USING THE SAME (17726494)

Main Inventor

Yi-Jung Chen

Brief explanation

This abstract describes a method for bonding semiconductor dies using a flip-chip technique. The process involves several steps: 

1. A wafer with multiple semiconductor dies is placed on an adhesive film held by a frame element. 2. A semiconductor die is lifted from the wafer using an ejector element. 3. The lifted die is then picked up by a collector element. 4. The collector element flips the die and aligns it with the desired position. 5. An alignment check is performed to determine the position of the die and the tolerance between the collector element and the die's center. 6. Based on the alignment check, the die with the collector element is transferred to a location underneath a bonder element. 7. The bonder element picks up the die from the collector element. 8. Finally, the bonder element bonds the die to a carrier.

Overall, this method provides a way to efficiently bond semiconductor dies using a flip-chip technique, ensuring accurate alignment and bonding.

Abstract

A flip-chip bonding method includes following operations. A wafer is provided with multiple semiconductor dies on an adhesive film held by a frame element. A semiconductor die is lifted up from the wafer by an ejector element. The semiconductor die is picked up with a collector element. The semiconductor die is flip-chipped with the collector element. An alignment check is performed to determine a position of the semiconductor die, so as to determine a process tolerance between a center of the collector element and a center of the semiconductor die. The semiconductor die with the collector element is transferred to a location underneath a bonder element based on the process tolerance of the alignment check. The semiconductor die is picked up from the collector element by the bonder element. The semiconductor die is bonded to a carrier by the bonder element.

INTEGRATED CIRCUIT PACKAGES AND METHOD OF FORMING THE SAME (18342749)

Main Inventor

Chia-Hao Hsu

Brief explanation

The abstract describes integrated circuit packages and the methods used to create them. These packages consist of multiple components, including at least one first die, a group of bumps, a second die, and a dielectric layer. The bumps are connected to the first die on one side, while the second die is connected to the first die on the opposite side. The dielectric layer is placed between the first die and the second die, covering the side of the first die.

Abstract

Provided are integrated circuit packages and methods of forming the same. An integrated circuit package includes at least one first die, a plurality of bumps, a second die and a dielectric layer. The bumps are electrically connected to the at least one first die at a first side of the at least one first die. The second die is electrically connected to the at least one first die at a second side of the at least one first die. The second side is opposite to the first side of the at least one first die. The dielectric layer is disposed between the at least one first die and the second die and covers a sidewall of the at least one first die.

PACKAGE STRUCTURE (17727841)

Main Inventor

Lipu Kris Chuang

Brief explanation

The abstract describes a package structure that includes a chip stacking structure, a thermal enhance component, and an insulating encapsulant. The thermal enhance component is placed on top of the chip stacking structure and is thermally connected to it. The thermal enhance component has a larger size in one direction compared to the chip stacking structure. The first insulating encapsulant surrounds both the thermal enhance component and the chip stacking structure.

Abstract

A package structure including a chip stacking structure, a thermal enhance component and a first insulating encapsulant is provided. The thermal enhance component is stacked over and thermally coupled to the chip stacking structure, wherein a first lateral dimension of the thermal enhance component is greater than a second lateral dimension of the chip stacking structure. The first insulating encapsulant laterally encapsulates the thermal enhance component and the chip stacking structure.

SEMICONDUCTOR STRUCTURE HAVING PHOTONIC DIE AND ELECTRONIC DIE (18342755)

Main Inventor

Hsien-Wei Chen

Brief explanation

The abstract describes a semiconductor structure that consists of two main components: an encapsulated electronic die and a photonic die. The electronic die is covered by an insulating layer, and the photonic die is connected to the encapsulated die. The photonic die includes an optical device near its edge coupling facet. In a top-down view, the boundary of the electronic die is contained within the boundary of the insulating layer, and the boundary of the insulating layer is contained within the boundary of the photonic die.

Abstract

A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18215059)

Main Inventor

Chia-Wen CHANG

Brief explanation

This abstract describes a semiconductor device that consists of a first channel region on a substrate and a first gate structure on top of the channel region. The gate structure includes multiple layers, including a gate dielectric layer, a lower conductive gate layer, a ferroelectric material layer, and an upper conductive gate layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower conductive gate layer, and it has a U-shape cross section.

Abstract

A semiconductor device includes a first channel region disposed over a substrate, and a first gate structure disposed over the first channel region. The first gate structure includes a gate dielectric layer disposed over the channel region, a lower conductive gate layer disposed over the gate dielectric layer, a ferroelectric material layer disposed over the lower conductive gate layer, and an upper conductive gate layer disposed over the ferroelectric material layer. The ferroelectric material layer is in direct contact with the gate dielectric layer and the lower gate conductive layer, and has a U-shape cross section.

SEMICONDUCTOR DEVICES WITH GATE ISOLATION STRUCTIONS AND METHODS OF MANUFACTURING THEREOF (18345068)

Main Inventor

Ya-Yi Tsai

Brief explanation

This abstract describes a semiconductor device that consists of two semiconductor fins and a dielectric fin placed between them. There is a gate isolation structure positioned above the dielectric fin. The device also includes a metal gate layer that runs perpendicular to the semiconductor fins, with one part covering the first semiconductor fin and another part covering the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, with the central portion extending closer to the dielectric fin compared to the side portions.

Abstract

A semiconductor device includes a first semiconductor fin and a second semiconductor fin extending along a first direction. The semiconductor device includes a dielectric fin, extending along the first direction, that is disposed between the first and second semiconductor fins. The semiconductor device includes a gate isolation structure vertically disposed above the dielectric fin. The semiconductor device includes a metal gate layer extending along a second direction perpendicular to the first direction, wherein the metal gate layer includes a first portion straddling the first semiconductor fin and a second portion straddling the second semiconductor fin. The gate isolation structure has a central portion and one or more side portions, the central portion extends toward the dielectric fin a further distance than at least one of the one or more side portions.

SEMICONDUCTOR DEVICE INCLUDING A CAPACITOR (18215707)

Main Inventor

Hong-Yang CHEN

Brief explanation

The abstract describes a capacitor structure used in a power semiconductor device. The structure includes a semiconductor substrate and an isolation insulating layer that has a ring shape and forms an opening in the center. On top of the isolation layer, there is a first electrode, followed by a dielectric layer, and finally a second electrode. This capacitor structure is designed to be used in power semiconductor devices.

Abstract

A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

MULTI-LATERAL RECESSED MIM STRUCTURE (18342861)

Main Inventor

Alexander Kalnitsky

Brief explanation

The abstract describes an integrated chip that has a layered structure called a dielectric stack. The dielectric stack has multiple layers arranged in a specific pattern. The chip also has recessed areas on the side of the dielectric stack at different heights. These recessed areas are lined with a structure called a capacitor, which consists of conductive electrodes separated by a special material called a capacitor dielectric.

Abstract

The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

EPITAXIAL STRUCTURES GROWN ON MATERIAL WITH A CRYSTALLOGRAPHIC ORIENTATION OF {110} ([[US Patent Application 17660818. EPITAXIAL STRUCTURES GROWN ON MATERIAL WITH A CRYSTALLOGRAPHIC ORIENTATION OF {110} simplified abstract|17660818]])

Main Inventor

Wei-Min Liu

Brief explanation

The abstract describes a method for creating a specific type of semiconductor structure called an epitaxial structure. The method involves starting with a fin structure made of a semiconductor material that has a specific crystallographic orientation. A portion of the fin structure is then etched to expose a sidewall of the semiconductor material. An epitaxial structure is then grown on this sidewall, and it has facets with the same crystallographic orientation as the original semiconductor material.

Abstract

Provided is an epitaxial structure and a method for forming such a structure. The method includes forming a fin structure on a substrate, wherein the fin structure includes a semiconductor material having substantially a {110} crystallographic orientation. The method includes etching a portion of the fin structure to expose a sidewall portion of the semiconductor material. Further, the method includes growing an epitaxial structure on the sidewall of the semiconductor material, wherein the epitaxial structure propagates with facets having a {110} crystallographic orientation.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17726522)

Main Inventor

Ren-Kai Chen

Brief explanation

This abstract describes a method of forming a semiconductor device. The method involves creating a structure called an epitaxial source/drain (S/D) next to a gate structure. A dielectric structure is then formed over the gate and epitaxial S/D structures. A trench is made in the dielectric structure to expose a part of the epitaxial S/D structure. A contact feature is formed from this exposed part within the trench. A S/D contact is also formed in the trench to connect with the contact feature. To create the contact feature, a metallic layer is formed in the trench and then subjected to a thermal process. After this process, some metallic residues are left on the sidewall of a spacer in the dielectric structure within the trench. These residues are removed using a wet etching process, while keeping the spacer intact.

Abstract

A method of forming a semiconductor device includes forming an epitaxial source/drain (S/D) structure adjacent to a gate structure; forming a dielectric structure over the gate and epitaxial S/D structures; forming a trench in the dielectric structure to accessibly expose a portion of the epitaxial S/D structure; forming a contact feature from the portion of the epitaxial S/D structure within the trench; and forming a S/D contact in the trench to be in contact with the contact feature overlying the epitaxial S/D structure. Forming the contact feature includes forming a metallic layer in the trench; performing a thermal process on the metallic layer to form the contact feature, where after the thermal process, metallic residues remain on a sidewall of a spacer of the dielectric structure in the trench; and removing the metallic residues by using a wet etching process, wherein the spacer of the dielectric structure remains substantially intact.

SEMICONDUCTOR GATE AND CONTACT FORMATION (17660241)

Main Inventor

Hsin-Han TSAI

Brief explanation

The abstract describes a method of annealing ruthenium in a metal gate or middle end of line structure to reduce or eliminate seams. This annealing process improves the electrical performance by decreasing the resistivity of the structure. It also helps in achieving a more even deposition profile, leading to a uniform gate height after etching. This increases the number of functional metal gates and improves the yield during the production of electronic devices.

Abstract

Ruthenium of a metal gate (MG) and/or a middle end of line (MEOL) structure is annealed to reduce, or even eliminate, seams after the ruthenium is deposited. Because the annealing reduces (or removes) seams in deposited ruthenium, electrical performance is increased because resistivity of the MG and/or the MEOL structure is decreased. Additionally, for MGs, the annealing generates a more even deposition profile, which results in a timed etching process producing a uniform gate height. As a result, more of the MGs will be functional after etching, which increases yield during production of the electronic device.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17876331)

Main Inventor

Shang-Wen CHANG

Brief explanation

This abstract describes a method of manufacturing a semiconductor device, specifically a field effect transistor (FET) with a metal gate structure. The process involves forming a first frontside contact between dummy metal gate structures over an isolation insulating layer. A frontside wiring layer is then formed over the first frontside contact. Next, a portion of the substrate is removed from the backside, exposing the bottom of the isolation insulating layer. A first opening is created in the isolation insulating layer, starting from the bottom, to expose the bottom of the first frontside contact. Finally, a first backside contact is formed by filling the first opening with a conductive material, which connects the first frontside contact.

Abstract

In a method of manufacturing a semiconductor device, a field effect transistor (FET) having a metal gate structure, a source and a drain over a substrate is formed. A first frontside contact disposed between dummy metal gate structures is formed over an isolation insulating layer. A frontside wiring layer is formed over the first frontside contact. A part of the substrate is removed from a backside of the substrate so that a bottom of the isolation insulating layer is exposed. A first opening is formed in the isolation insulating layer from the bottom of the isolation insulating layer to expose a bottom of the first frontside contact. A first backside contact is formed by filling the first opening with a conductive material to connect the first frontside contact.

SEMICONDUCTOR STRUCTURE (17727846)

Main Inventor

Yen-Ching Wu

Brief explanation

This abstract describes a semiconductor structure that includes various components such as an insulator, a semiconductor fin, a gate stack, a gate contact, a source/drain material, and a source/drain contact structure. The semiconductor fin sticks out from the insulator, and the gate stack is placed on both the semiconductor fin and the insulator. The gate contact is connected to the gate stack, while the source/drain material is placed on the semiconductor fin. The source/drain contact structure is connected to the source/drain material. The semiconductor fin extends in one direction, while the gate stack extends in a different direction. There is a specific offset (S) between the gate contact and the source/drain contact structure, which must satisfy a certain condition based on the width of the semiconductor fin (W) and the dimension of the gate contact (D).

Abstract

A semiconductor structure includes an insulator, a semiconductor fin, a gate stack, a gate contact, a source/drain material, and a source/drain contact structure. The semiconductor fin protrudes from the insulator. The gate stack is disposed on the semiconductor fin and the insulator. The gate contact is disposed on and electrically connected to the gate stack. The source/drain material is disposed on the semiconductor fin. The source/drain contact structure is disposed on and electrically connected to the source/drain material. The semiconductor fin extends along a first direction, the gate stack extends along a second direction different from the first direction. An offset S in the second direction between the gate contact and the source/drain contact structure satisfies: 0<S≤(W/2+D/2), wherein W is a width of the semiconductor fin, and D is a dimension of the gate contact.

TOPOLOGY SELECTIVE AND SACRIFICIAL SILICON NITRIDE LAYER FOR GENERATING SPACERS FOR A SEMICONDUCTOR DEVICE DRAIN (18342048)

Main Inventor

Tzu-Yang HO

Brief explanation

The abstract describes a method for forming a metal drain in a semiconductor device. The method involves creating a layer of silicon nitride in an opening of the device and on its surface. Another layer of silicon nitride is then formed on top of the first layer, acting as a sacrificial layer. The second layer is removed from the sides of the first layer in the opening. Both layers are then removed from the bottom of the opening. Finally, a metal layer is deposited in the opening to create the metal drain.

Abstract

A method may include forming a first silicon nitride layer in an opening of the semiconductor device and on a top surface of the semiconductor device, wherein the semiconductor device includes an epitaxial source/drain and a metal gate. The method may include forming a second silicon nitride layer on the first silicon nitride layer, as a sacrificial layer, and removing the second silicon nitride layer from sidewalls of the first silicon nitride layer formed in the opening. The method may include removing the second silicon nitride layer and the first silicon nitride layer formed at a bottom of the opening, and depositing a metal layer in the opening to form a metal drain in the opening of the semiconductor device.

FIELD-EFFECT TRANSISTOR AND METHOD OF FORMING THE SAME (18344581)

Main Inventor

Chen-Ping Chen

Brief explanation

The abstract describes a semiconductor device that includes a substrate made of a semiconductor material. The device also has a conduction channel of a transistor located above the substrate, and both the channel and the substrate are made of the same semiconductor material. The device further includes a source/drain region that extends from one end of the conduction channel. The source/drain region is connected to the conduction channel and is isolated from the substrate by a dielectric structure.

Abstract

A semiconductor device is disclosed. The semiconductor device includes a substrate including a semiconductor material. The semiconductor device includes a conduction channel of a transistor disposed above the substrate. The conduction channel and the substrate include a similar semiconductor material. The semiconductor device includes a source/drain region extending from an end of the conduction channel. The semiconductor device includes a dielectric structure. The source/drain region is electrically coupled to the conduction channel and electrically isolated from the substrate by the dielectric structure.

INTEGRATED CIRCUIT STRUCTURE (18340454)

Main Inventor

Wei-Hao LU

Brief explanation

This abstract describes a method for manufacturing an integrated circuit (IC) structure. The process involves etching recesses in a substrate and then forming a sacrificial epitaxial plug in one of the recesses. Epitaxial features are then formed in both recesses, with the first epitaxial feature being positioned over the sacrificial plug. Source/drain epitaxial structures are formed over the epitaxial features, and a gate structure is placed between them. The sacrificial plug and the first epitaxial feature are then removed, creating an opening that exposes the backside of the first source/drain epitaxial structure. Finally, a backside via is formed in this opening.

Abstract

A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (17726812)

Main Inventor

An-Hung TAI

Brief explanation

This abstract describes a method of manufacturing a semiconductor device. It involves creating an opening in a dielectric layer and forming a lower conductive layer within the opening. The lower conductive layer is then recessed to create a space. A blanket conductive layer is deposited over the recessed lower conductive layer, as well as on the sidewall of the space and the upper surface of the dielectric layer. Some of the blanket conductive layer on the sidewall and upper surface is removed, resulting in the formation of an upper conductive layer on top of the lower conductive layer. Finally, a cap insulating layer is formed over the upper conductive layer within the space. The blanket conductive layer is created using physical vapor deposition.

Abstract

In a method of manufacturing a semiconductor device, a lower conductive layer is formed in an opening formed in a dielectric layer, and the lower conductive layer is recessed to form a space. A blanket conductive layer is formed over the recessed lower conductive layer in the space, a sidewall of the space and an upper surface of the dielectric layer. Part of the blanket conductive layer formed on the sidewall of the opening and the upper surface of the dielectric layer is removed, thereby forming a upper conductive layer on the lower conductive layer, and a cap insulating layer is formed over the upper conductive layer in the space. The blanket conductive layer is formed by physical vapor deposition.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17727737)

Main Inventor

Jenn-Gwo HWU

Brief explanation

This abstract describes a semiconductor device that consists of three main components: a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is located on top of the substrate, and the sensing pad is in direct contact with the dielectric layer. The first and second sensing electrodes are also in contact with the dielectric layer and surround the sensing pad. Importantly, the distance between the first and second sensing electrodes is greater than the distance between the sensing pad and the first sensing electrode. The transistor is positioned on top of the substrate, and its gate is connected to the sensing pad.

Abstract

A semiconductor device includes a substrate, a sensing device, and a transistor. The sensing device includes a dielectric layer, a sensing pad, a first sensing electrode, and a second sensing electrode. The dielectric layer is over the substrate. The sensing pad is over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode are over and in contact with the dielectric layer. The first sensing electrode and the second sensing electrode surround the sensing pad, and a distance between the first sensing electrode and the second sensing electrode is greater than a distance between the sensing pad and the first sensing electrode. The transistor is over the substrate. A gate of the transistor is connected to the sensing pad.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18216560)

Main Inventor

Chun-Sheng LIANG

Brief explanation

This abstract describes a method of fabricating semiconductors. It involves several steps, including forming a dielectric layer on a substrate, creating a dummy gate structure on the dielectric layer, and etching a portion of the dielectric layer to form a dielectric etch back region. A spacer element is then formed on the etched region, and a recessed portion is created in the substrate. A strained material is selectively grown over the recessed portion to form a strained recessed region. The dummy gate structure and the dummy gate dielectric region are removed, and a gate electrode layer and a gate dielectric layer are formed.

Abstract

A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

GATE ALL AROUND STRUCTURE WITH ADDITIONAL SILICON LAYER AND METHOD FOR FORMING THE SAME (18344057)

Main Inventor

Chen-Han WANG

Brief explanation

The abstract describes a method for manufacturing a semiconductor structure. The process involves stacking layers of different semiconductor materials on a substrate and then patterning them to create fin structures. An insulating layer is then formed around the fin structures, followed by the creation of a dielectric fin structure. Source/drain structures are formed on the first fin structure, and a semiconductor layer is added on top. This semiconductor layer is then oxidized to form an oxide layer. Finally, a second source/drain structure is formed on the second fin structure.

Abstract

Methods for manufacturing a semiconductor structure are provided. The method includes alternately stacking first semiconductor material layers and second semiconductor layers over a substrate and patterning the first semiconductor material layers and the second semiconductor layers to form a first fin structure and a second fin structure. The method also includes forming an insulating layer around the first fin structure and the second fin structure and forming a dielectric fin structure over the insulating layer and spaced apart from the first fin structure and the second fin structure. The method also includes forming a first source/drain structure attached to the first fin structure and forming a semiconductor layer covering the first source/drain structure. The method also includes oxidizing the semiconductor layer to form an oxide layer and forming a second source/drain structure attached to the second fin structure after the oxide layer is formed.

FULL WELL CAPACITY FOR IMAGE SENSOR (18335171)

Main Inventor

Kai-Yun Yang

Brief explanation

The abstract describes a type of image sensor that uses a photodetector placed in a semiconductor substrate. The photodetector consists of a first doped region with a specific type of dopant. A deep well region is present from the back-side surface of the substrate to the top surface of the first doped region. A second doped region is located within the substrate and is adjacent to the first doped region. The second doped region and the deep well region have a different type of dopant compared to the first doped region. An isolation structure is placed within the substrate, extending from the back-side surface to a point below it. A doped liner, made of the second dopant, is present between the isolation structure and the second doped region.

Abstract

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.

IMAGE SENSOR STRUCTURE (17835049)

Main Inventor

Hsiang-Lin Chen

Brief explanation

The abstract describes the invention of image sensors and the methods used to create them. These image sensors consist of a silicon substrate with a germanium region embedded in it. A doped semiconductor isolation layer separates the silicon substrate and the germanium region. There is a heavily p-doped region on top of the germanium region and a heavily n-doped region on top of the silicon substrate. Below the germanium region, there is a first n-type well, and below the heavily n-doped region, there is a second n-type well. Finally, there is a deep n-type well that is in contact with both the first and second n-type wells.

Abstract

Image sensors and methods of forming the same are provided. An image sensor according to the present disclosure includes a silicon substrate, a germanium region disposed in the silicon substrate, a doped semiconductor isolation layer disposed between the silicon substrate and the germanium region, a heavily p-doped region disposed on the germanium region, a heavily n-doped region disposed on the silicon substrate, a first n-type well disposed immediately below the germanium region, a second n-type well disposed immediately below the heavily n-doped region, and a deep n-type well disposed below and in contact with the first n-type well and the second n-type well.

DUAL MODE SUPPLY CIRCUIT AND METHOD (18343425)

Main Inventor

Wei LI

Brief explanation

The abstract describes a circuit that includes various components such as a power supply node, reference node, output node, transistors, and an amplifier. The circuit is designed to perform specific functions based on different signals received. It utilizes passive devices and switching devices to control the flow of signals between different nodes in the circuit. The abstract does not provide specific details about the purpose or application of the circuit.

Abstract

A circuit includes a power supply node, a reference node, an output node, a first transistor coupled between the power supply and output nodes, and an amplifier including a non-inverting input coupled to the power supply node through a first passive device, an inverting input coupled to the reference node through a second passive device, and an output coupled to a gate of the first transistor. A first inverter is coupled between the output and reference nodes and generates a mode control signal responsive to a mode select signal, a first switching device is configured to, responsive to the mode control signal, selectively couple the non-inverting input of the amplifier to the reference node through a third passive device, and a second switching device is configured to, responsive to the mode control signal, selectively couple the inverting input of the amplifier to the output node through a fourth passive device.

METHOD FOR OPERATING SEMICONDUCTOR DEVICE INCLUDING MULTI-GATED I/O SYSTEM (18218080)

Main Inventor

Shao-Te WU

Brief explanation

The abstract describes a method for operating a power-on signal generator. This generator includes a load that reduces sensitivity to variations in power supply, as well as a transistor and resistors. The method involves monitoring a voltage and when it exceeds a certain threshold, turning on the transistor. This action pulls down various voltages, including the power-on signal, to a logical low value.

Abstract

A method of operating a power-on (PO) signal generator (which generates a PO signal and includes a supply-variation sensitivity-reducing (SVSR) load coupled between a first reference voltage and a first node, and a first transistor coupled between the first node and a second reference voltage, the SVSR load including a first resistor coupled between the first reference voltage and a second node, and a second transistor coupled between the second node and the first node, each of a control input of the SVSR load and a gate terminal the first transistor being coupled to a monitored voltage) includes: when the monitored voltage rises above a threshold voltage of the first transistor, turning on the first transistor, and pulling first and second voltages correspondingly on the first and second nodes, a third voltage of the second transistor, and the PO signal down to a logical low value.

Automatic Hybrid Oscillator Gain Adjustor Circuit (18344120)

Main Inventor

Tsung-Hsien Tsai

Brief explanation

The abstract describes an automatic gain adjustor for a hybrid oscillator that can overcome the frequency limitations of hybrid phase lock loops (PLLs). It explains that the automatic gain adjustor includes a hybrid oscillator that receives a coarse tuning signal and a gain adjustment signal to generate an output signal within the specified frequency range of the hybrid PLL. Additionally, it mentions the inclusion of a fine tuning array that receives fine tuning selection signals and generates a gain adjustment signal for the hybrid oscillator. This allows the gain of the hybrid oscillator to be adjusted based on the operating frequency range.

Abstract

An automatic gain adjustor for a hybrid oscillator can be employed to overcome the frequency limitations of hybrid phase lock loops (PLLs). For example, an automatic gain adjustor for a hybrid oscillator can include a hybrid oscillator that is configured to receive a coarse tuning signal and a gain adjustment signal and generate an output signal with any frequency within the specified frequency range of the hybrid PLL. The automatic gain adjustor for a hybrid PLL may further include a fine tuning array that receives one or more fine tuning selection signals and generates a gain adjustment signal that is received by the hybrid oscillator. The fine tuning array generates a gain adjustment signal to adjust the gain of the hybrid oscillator according to an operating frequency range of the hybrid oscillator.

METHOD AND APPARATUS FOR MONITORING AN EXTREME ULTRAVIOLET RADIATION SOURCE (17727479)

Main Inventor

Yu-Kuang SUN

Brief explanation

The Inline Tin Stream Monitor (ITSM) system is designed to address the issue of unexpected material depletion causing long periods of downtime. It achieves this by accurately measuring the amount of tin introduced through an in-line refill system. Additionally, it estimates the remaining runtime by measuring changes in pressure levels before and after the refill process. This system aims to prevent disruptions in operations and improve efficiency by providing precise monitoring and estimation of tin levels.

Abstract

In order to prevent long down-time that occurs with unexpected material depletion, an Inline Tin Stream Monitor (ITSM) system precisely measures the tin amount introduced by an in-line refill system and precisely estimates remaining runtime by measuring pressure level changes before and after in-line refill.

FLOATING GATE TEST STRUCTURE FOR EMBEDDED MEMORY DEVICE (18344161)

Main Inventor

Hung-Ling Shih

Brief explanation

The abstract describes a method for creating an integrated circuit (IC) that includes memory cell structures and memory test structures. The memory test structures consist of a dummy control gate and a dummy floating gate, which are separated from the substrate. The method also involves forming a conductive floating gate test contact along the sides of the dummy control gate and the dummy floating gate.

Abstract

Various embodiments of the present application are directed to a method for forming an integrated circuit (IC) comprising forming a multilayer film to form a plurality of memory cell structures disposed over a substrate and a plurality of memory test structures next to the memory cell structures. A memory test structure comprises a dummy control gate separated from the substrate by a dummy floating gate. The method further comprises forming a conductive floating gate test contact via along sidewalls of the dummy control gate and the dummy floating gate.

INTEGRATED CHIP WITH A GATE STRUCTURE DISPOSED WITHIN A TRENCH (18335168)

Main Inventor

Yong-Sheng Huang

Brief explanation

The abstract describes an integrated chip that includes a substrate with a trench on its front-side surface. The trench is filled with a gate structure that extends along the sidewalls of the trench and reaches the upper surface of the substrate. The chip also has two source/drain regions located on the front-side surface of the substrate, with the gate structure positioned between them. The bottom surface of the gate structure is below the bottom surface of the first source/drain region.

Abstract

The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure fills the trench and extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.

MEMORY DEVICE COMPRISING CONDUCTIVE PILLARS (18341764)

Main Inventor

Yu-Wei Jiang

Brief explanation

The abstract describes a memory device that consists of multiple layers stacked on top of each other. These layers include conductive and dielectric layers. The memory material layer is located between the channel layer and the conductive and dielectric layers. The device also includes conductive pillars that are aligned in a direction perpendicular to the layers.

Abstract

A memory device includes a multi-layer stack, a channel layer, a memory material layer and a memory material layer. The multi-layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately along a first direction. The memory material layer is disposed between the channel layer and each of the conductive layers and the dielectric layers. The conductive pillars extend in the first direction, wherein the at least three conductive pillars are aligned along a second direction substantially perpendicular to the first direction.

THREE-DIMENSIONAL MEMORY DEVICE WITH WORD LINES EXTENDING THROUGH SUB-ARRAYS, SEMICONDUCTOR DEVICE INCLUDING THE SAME AND METHOD FOR MANUFACTURING THE SAME (18346278)

Main Inventor

Meng-Han Lin

Brief explanation

The abstract describes a memory device and a semiconductor device, as well as the methods used to manufacture them. The memory device consists of several components, including a stacking structure, a switching layer, channel layers, and pairs of conductive pillars. The stacking structure is made up of alternating isolation layers and word lines, and it extends in a specific direction. It has a staircase portion and a connection portion at the edge, which is not shaped like a staircase. The switching layer covers the sidewall of the stacking structure, while the channel layers cover the sidewall of the switching layer. These channel layers are spaced apart from each other in the same direction as the stacking structure. The pairs of conductive pillars are located on the substrate and are in contact with the switching layer through the channel layers.

Abstract

A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device includes a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.

FIN STRUCTURE FOR INCREASING PERFORMANCE OF FERROELECTRIC MEMORY DEVICE (17724937)

Main Inventor

Kuen-Yi Chen

Brief explanation

The abstract describes an integrated chip that includes a fin structure extending vertically from a semiconductor substrate. The fin structure extends laterally in one direction and is covered by a ferroelectric memory stack. The ferroelectric memory stack extends laterally in a different direction, perpendicular to the fin structure. The stack consists of an upper electrode and a ferroelectric layer that covers the sidewalls and upper surface of the fin structure.

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip including a fin structure extending vertically from a semiconductor substrate. The fin structure continuously extends laterally along a first direction. A ferroelectric memory stack overlies the fin structure and continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The ferroelectric memory stack includes an upper electrode overlying a ferroelectric layer. The ferroelectric layer extends along opposing sidewalls and an upper surface of the fin structure.

Defect Reduction Through Scheme Of Conductive Pad Layer And Capping Layer (17890883)

Main Inventor

Ching Ju Yang

Brief explanation

This abstract describes an interconnect structure that consists of two interconnect elements. The first interconnect element is connected to a conductive pad layer, which is covered by a capping layer made of titanium nitride. A dielectric layer is placed on top of the capping layer. There is a conductive contact that goes through the dielectric and capping layers, connecting to the first interconnect element through the conductive pad layer. Additionally, there is a conductive via that goes through the dielectric layer, connecting to the second interconnect element.

Abstract

An interconnect structure includes at least a first interconnect element and a second interconnect element. A conductive pad layer is disposed over, and electrically coupled to, the first interconnect element. A capping layer is disposed over the conductive pad layer. The capping layer includes titanium nitride. A dielectric layer is disposed over the capping layer. A conductive contact extends vertically through at least a first portion of the dielectric layer and the capping layer. The conductive contact is coupled to the first interconnect element through the conductive pad layer. A conductive via extends vertically through at least a second portion of the dielectric layer. The conductive via is coupled to the second interconnect element.

MAGNETIC MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17726981)

Main Inventor

Hung-Cho WANG

Brief explanation

This abstract describes a memory device that has a memory unit and a shielding element. The memory unit consists of a bottom electrode, a memory element, and a top electrode. The shielding element is placed on the memory unit to redirect any external magnetic field away from the memory element.

Abstract

A memory device includes a memory unit and a shielding element disposed on the memory unit. The memory unit includes a bottom electrode, a memory element disposed on the bottom electrode, and a top electrode disposed on the memory element. The shielding element is disposed on the memory unit to deviate an external magnetic field away from the memory element.

DATA STORAGE STRUCTURE FOR IMPROVING MEMORY CELL RELIABILITY (18335176)

Main Inventor

Hai-Dang Trinh

Brief explanation

The abstract describes an integrated chip that includes multiple layers of conductive and dielectric materials. The chip has a first conductive structure on top of a substrate, a second conductive structure on top of the first one, and a data storage structure between them. The data storage structure consists of three dielectric layers with different bandgaps.

Abstract

Various embodiments of the present disclosure are directed towards an integrated chip. A first conductive structure overlies a substrate. A second conductive structure overlies the first conductive structure. A data storage structure is disposed between the first and second conductive structures. The data storage structure includes a first dielectric layer, a second dielectric layer, and a third dielectric layer. Respective bandgaps of the first, second, and third dielectric layers are different from one another.