US Patent Application 18333392. STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME simplified abstract

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STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Chih-Yu Lin of Hsinchu (TW)


Wei-Cheng Wu of Hsinchu (TW)


Kao-Cheng Lin of Hsinchu (TW)


Yen-Huei Chen of Hsinchu (TW)


STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18333392 Titled 'STATIC RANDOM ACCESS MEMORY AND METHOD OF CONTROLLING THE SAME'

Simplified Explanation

The abstract describes a type of memory called static random access memory (SRAM) that has two memory cell arrays. It also includes various components such as word lines, bit lines, driver circuits, and supplementary driver circuits. During a write operation, the first supplementary driver circuit pulls the voltage of a signal on the bit line or its complement to a specific level. The second supplementary driver circuit senses the voltage of the signal and includes a pass-gate transistor that is connected to a reference voltage supply and a first node.


Original Abstract Submitted

A static random access memory includes a first and second memory cell array, a first word line, a bit line, a bit line bar, a primary driver circuit, and a first and second supplementary driver circuit. The first supplementary driver circuit is configured to pull a voltage of a first signal of the bit line or a second signal of the bit line bar to a first voltage level during a write operation in response to a supplementary driver circuit enable signal. The second supplementary driver circuit is configured to sense the voltage of the first or second signal. The second supplementary driver circuit includes a first pass-gate transistor. A first terminal of the first pass-gate transistor is coupled to a reference voltage supply. A second terminal of the first pass-gate transistor is electrically floating. A third terminal of the first pass-gate transistor is coupled to a first node.