US Patent Application 18340092. PAD STRUCTURE FOR ENHANCED BONDABILITY simplified abstract
Contents
PAD STRUCTURE FOR ENHANCED BONDABILITY
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Ru-Ying Huang of Taipei City (TW)
Yung-Ching Chen of Dali City (TW)
Yueh-Chiou Lin of Taichung County (TW)
Yian-Liang Kuo of Hsinchu City (TW)
PAD STRUCTURE FOR ENHANCED BONDABILITY - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18340092 Titled 'PAD STRUCTURE FOR ENHANCED BONDABILITY'
Simplified Explanation
The abstract describes a pad with high strength and bondability. It explains that the pad is part of an integrated chip and is connected to a substrate through an interconnect structure. The interconnect structure consists of wires and vias that are stacked between the pad and the substrate. The abstract also mentions a conductive structure, such as a wire bond, that extends through the substrate to the pad. This arrangement allows the pad to be inset into a passivation layer of the interconnect structure, which helps absorb stress on the pad. The pad also contacts the wires and vias at a top wire level, which is thicker and more tolerant to stress compared to other wire levels.
Original Abstract Submitted
Various embodiments of the present application are directed towards a pad with high strength and bondability. In some embodiments, an integrated chip comprises a substrate, an interconnect structure, a pad, and a conductive structure. The interconnect structure adjoins the substrate and comprises wires and vias. The wires and the vias are stacked between the pad and the substrate. The conductive structure (e.g., a wire bond) extends through the substrate to the pad. By arranging the wires and the vias between the pad and the substrate, the pad may be inset into a passivation layer of the interconnect structure and the passivation layer may absorb stress on the pad. Further, the pad may contact the wires and the vias at a top wire level. A thickness of the top wire level may exceed a thickness of other wire levels, whereby the top wire level may be more tolerant to stress.
