US Patent Application 18345071. DUO-LEVEL WORD LINE DRIVER simplified abstract
Contents
DUO-LEVEL WORD LINE DRIVER
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Po-Hao Lee of Hsinchu City (TW)
Chia-Fu Lee of Hsinchu City (TW)
DUO-LEVEL WORD LINE DRIVER - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18345071 Titled 'DUO-LEVEL WORD LINE DRIVER'
Simplified Explanation
The abstract describes a circuit that consists of two transistors connected to each other in a specific way. The first transistor's source and the second transistor's source are connected to a power supply. The gate of the first transistor is connected to the drain of the second transistor at a first node, and the gate of the second transistor is connected to the drain of the first transistor at a second node.
This circuit is designed to provide different levels of voltage to a memory cell. It can directly connect the power supply, which is set at a first level, to the memory cell through the second transistor and a third transistor, in order to provide a first level of voltage to the memory cell. Similarly, it can directly connect the power supply, which is set at a second level, to the memory cell through the second transistor and the third transistor, in order to provide a second level of voltage to the memory cell.
In summary, this circuit allows for the provision of different voltage levels to a memory cell by directly connecting the power supply to the memory cell through specific transistors.
Original Abstract Submitted
A circuit includes a first transistor and a second transistor cross-coupled with each other such that a source of the first transistor and a source of the second transistor are connected to a power supply, a gate of the first transistor is connected to a drain of the second transistor at a first node, a gate of the second transistor is connected to a drain of the first transistor at a second node. The circuit can provide a first level of a word line voltage to the memory cell by directly coupling the power supply configured at a first level to the memory cell through the second transistor and a third transistor, and provide a second level of the word line voltage by directly coupling the power supply configured at a second level to the memory cell through the second transistor and the third transistor.
