US Patent Application 18216560. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract
Contents
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Chun-Sheng Liang of Puyan Township (TW)
Shih-Hsun Chang of Hsinchu (TW)
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18216560 Titled 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF'
Simplified Explanation
This abstract describes a method of fabricating semiconductors. It involves several steps, including forming a dielectric layer on a substrate, creating a dummy gate structure on the dielectric layer, and etching a portion of the dielectric layer to form a dielectric etch back region. A spacer element is then formed on the etched region, and a recessed portion is created in the substrate. A strained material is selectively grown over the recessed portion to form a strained recessed region. The dummy gate structure and the dummy gate dielectric region are removed, and a gate electrode layer and a gate dielectric layer are formed.
Original Abstract Submitted
A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.
