US Patent Application 18335171. FULL WELL CAPACITY FOR IMAGE SENSOR simplified abstract

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FULL WELL CAPACITY FOR IMAGE SENSOR

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Kai-Yun Yang of Tainan City (TW)


Chun-Yuan Chen of Tainan City (TW)


Ching I Li of Tainan (TW)


FULL WELL CAPACITY FOR IMAGE SENSOR - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18335171 Titled 'FULL WELL CAPACITY FOR IMAGE SENSOR'

Simplified Explanation

The abstract describes a type of image sensor that uses a photodetector placed in a semiconductor substrate. The photodetector consists of a first doped region with a specific type of dopant. A deep well region is present from the back-side surface of the substrate to the top surface of the first doped region. A second doped region is located within the substrate and is adjacent to the first doped region. The second doped region and the deep well region have a different type of dopant compared to the first doped region. An isolation structure is placed within the substrate, extending from the back-side surface to a point below it. A doped liner, made of the second dopant, is present between the isolation structure and the second doped region.


Original Abstract Submitted

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed in a semiconductor substrate. The photodetector comprises a first doped region comprising a first dopant having a first doping type. A deep well region extends from a back-side surface of the semiconductor substrate to a top surface of the first doped region. A second doped region is disposed within the semiconductor substrate and abuts the first doped region. The second doped region and the deep well region comprise a second dopant having a second doping type opposite the first doping type. An isolation structure is disposed within the semiconductor substrate. The isolation structure extends from the back-side surface of the semiconductor substrate to a point below the back-side surface. A doped liner is disposed between the isolation structure and the second doped region. The doped liner comprises the second dopant.