US Patent Application 17724928. TESTING MODULE AND METHOD FOR USING THE SAME simplified abstract

From WikiPatents
Jump to navigation Jump to search

TESTING MODULE AND METHOD FOR USING THE SAME

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.


Inventor(s)

Jen-Yuan Chang of Hsinchu City (TW)


Kong-Beng Thei of Hsinchu County (TW)


Jung-Hui Kao of Hsinchu City (TW)


TESTING MODULE AND METHOD FOR USING THE SAME - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 17724928 Titled 'TESTING MODULE AND METHOD FOR USING THE SAME'

Simplified Explanation

This method involves the fabrication and testing of an integrated circuit on a wafer. The integrated circuit and a testing pattern are formed using the same process. A testing chip is connected to the testing pattern, and electrical properties of the pattern are detected to perform a testing process on the integrated circuit. Once testing is complete, an interconnection structure is formed over the integrated circuit, which includes conductive features that are connected to the circuit. Finally, the wafer is singulated into individual die through a process called singulation.


Original Abstract Submitted

A method includes forming an integrated circuit and a testing pattern over a die region of a wafer and a scribe line region of the wafer, respectively, in which the integrated circuit and the testing pattern are formed by a same fabrication process; connecting a via of a testing chip to a testing pad of the testing pattern; performing a testing process to the die region by detecting electrical properties of the testing pattern through the testing chip; after the testing process is completed, forming an interconnection structure over the integrated circuit, in which the interconnection structure includes conductive features electrically connected to the integrated circuit; and after the interconnection structure is formed over the integrated circuit performing an singulation process through the scribe line region of the wafer, such that the die region of the wafer is singulated into an individual die.