Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 12th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of device structures, materials, and fabrication processes. Here is a summary of the recent patents filed by TSMC:

- Patent 1: A semiconductor device that includes a transistor and an interconnect structure. The interconnect structure consists of multiple interlayer dielectric layers, a via, and a memory cell. The memory cell is connected to the via and positioned over the interlayer dielectric layers.

- Patent 2: A ferroelectric memory device that includes a bottom electrode, a ferroelectric structure, and a top electrode. The bottom electrode is made of molybdenum.

- Patent 3: An integrated chip that includes a gate electrode, a gate dielectric layer made of a ferroelectric material, an active structure made of a semiconductor material, and a capping structure made of a metal material.

- Patent 4: A memory device that includes a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is located on top of a substrate, and the resistance-switchable element is in contact with the semiconductor layer.

- Patent 5: A ferroelectric memory device that includes multiple layers stacked on a substrate. These layers include conductive and dielectric layers arranged alternately, with a ferroelectric layer placed between them. Oxygen scavenging layers act as a barrier between the ferroelectric layer and the conductive layers.

- Patent 6: A method for creating a memory device that involves forming stacks of word lines and insulating layers on a semiconductor substrate, creating a data storage layer and a channel layer on the sidewalls of the word line stacks, and forming source/drain contacts.

- Patent 7: A semiconductor memory device that includes metal lines and memory arrays. Each memory array includes two sets of thin film transistors (TFTs) connected in parallel, and switch transistors connected in series to the TFTs and metal lines.

- Patent 8: A memory device that includes multiple layers of gate electrodes and interconnects on a substrate. The device includes a first memory cell with source/drain conductive lines and a channel layer and memory layer on the sides of these lines.

- Patent 9: A system for generating a pulse width modulation (PWM) signal with a specific duty cycle. The system includes a square wave generator, a logic device, and multiple square wave signals.

- Patent 10: A device for electrostatic discharge (ESD) protection that includes an ESD detector, P-type and N-type transistors connected in series, a drive circuit, and protection circuits operating in different power domains.

Notable applications:

• Memory devices with improved performance and reliability.
• Ferroelectric memory devices with enhanced electrode materials.
• Integrated chips with ferroelectric gate dielectric layers.
• Memory devices with resistance-switchable elements.
• Memory devices with stacked layers and oxygen scavenging layers.
• Methods for fabricating memory devices with improved process efficiency.
• Semiconductor memory devices with parallel thin film transistors.
• Memory devices with barrier structures for improved performance.
• Systems for generating PWM signals with specific duty cycles.
• ESD protection devices with improved circuitry and power domain control.

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023

APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)

Main Inventor

Feng-Wei Kuo

Brief explanation

The abstract describes the invention of apparatuses for optical coupling and a communication system. One embodiment of the apparatus includes a substrate and a grating coupler. The grating coupler is placed on the substrate and consists of multiple coupling gratings arranged in a specific direction. These coupling gratings have gradually decreasing effective refractive indices along that direction.

Abstract

Disclosed are apparatuses for optical coupling and a system for communication. In one embodiment, an apparatus for optical coupling including a substrate and a grating coupler is disclosed. The grating coupler is disposed on the substrate and includes a plurality of coupling gratings arranged along a first direction, wherein effective refractive indices of the plurality of coupling gratings gradually decrease along the first direction.

PELLICLE FRAME WITH STRESS RELIEF TRENCHES (18335232)

Main Inventor

Kuo-Hao LEE

Brief explanation

The abstract describes a method of forming a photomask assembly with stress relief trenches in the pellicle frame. These trenches help to prevent damage to the pellicle by allowing the frame to deform along with the pellicle, reducing the amount of damage caused by the frame.

Abstract

A photomask assembly may be formed such that stress relief trenches are formed in a pellicle frame of the photomask assembly. The stress relief trenches may reduce or prevent damage to a pellicle that may otherwise result from deformation of the pellicle. The stress relief trenches may be formed in areas of the pellicle frame to allow the pellicle frame to deform with the pellicle, thereby reducing the amount damage to the pellicle caused by the pellicle frame.

PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18208794)

Main Inventor

Li-Po YANG

Brief explanation

The abstract describes a method for creating a pattern in a photoresist layer on a substrate. The process involves applying a photoresist layer containing a polymer onto the substrate. The photoresist layer is then selectively exposed to actinic radiation, which creates a hidden pattern. This latent pattern is then developed by applying a developer, which reveals the desired pattern on the photoresist layer.

Abstract

Method of forming pattern in photoresist layer includes forming photoresist layer over substrate, selectively exposing photoresist layer to actinic radiation forming latent pattern. Latent pattern is developed by applying developer to form pattern. Photoresist layer includes photoresist composition including polymer:

METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM (18326354)

Main Inventor

Chi YANG

Brief explanation

This abstract describes a method for performing a lithography process, which is a technique used in semiconductor manufacturing to create circuit layouts. The method involves several steps. First, a photoresist layer is formed over a substrate. Then, a source vessel is provided with target droplets, and a controller sends a control signal to generate plasma by irradiating the target droplets with laser pulses. The plasma generates extreme ultraviolet (EUV) radiation when the temperature of the source vessel is within a certain threshold. The EUV radiation is then directed onto the photoresist layer to create a patterned photoresist layer. Finally, the patterned photoresist layer is developed and etched to form a circuit layout.

Abstract

A method for performing a lithography process is provided. The method includes forming a photoresist layer over a substrate, providing a plurality of target droplets to a source vessel, and providing a plurality of first laser pulses according to a control signal provided by a controller to irradiate the target droplets in the source vessel to generate plasma as an EUV radiation. The plasma is generated when the control signal indicates a temperature of the source vessel is within a temperature threshold value. The method further includes directing the EUV radiation from the source vessel to the photoresist layer to form a patterned photoresist layer and developing and etching the patterned photoresist layer to form a circuit layout.

EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION (17717709)

Main Inventor

I-Hsiung HUANG

Brief explanation

The abstract describes an apparatus used in extreme ultra violet (EUV) lithography. It consists of a light source that produces an EUV light beam, a scanner that receives the light from the light source and directs it to a reticle stage, and a debris catcher positioned on the EUV beam path between the light source and the scanner. The debris catcher is made up of a network membrane that contains numerous nano-fibers.

Abstract

An extreme ultra violet (EUV) lithography apparatus includes a light source that generates an EUV light beam, a scanner that receives the light from a junction with the light source and directs the light to a reticle stage, and a debris catcher disposed on a EUV beam path between the light source and the scanner. The debris catcher includes a network membrane including a plurality of nano-fibers.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME (18335505)

Main Inventor

Ke-Ying SU

Brief explanation

This abstract describes a method for manufacturing a semiconductor device. It involves generating a layout diagram that includes various layout cells. Instead of calculating the parasitic capacitance (PC) for each cell individually, the method searches a database of predefined cells and their corresponding PC descriptions. If a predefined cell is found that closely matches a candidate cell, the PC description of the matching predefined cell is assigned to the candidate cell. This approach simplifies the manufacturing process by avoiding the need for discrete calculations of PC for each cell.

Abstract

A method of manufacturing a semiconductor device, a corresponding layout diagram being stored on a non-transitory computer-readable medium, the layout diagram including layout cells, the method including generating the layout diagram including: for a candidate cell amongst the layout cells in the layout diagram, avoiding a discrete calculation of a corresponding parasitic capacitance (PC) description including, within a database which stores predefined cells and corresponding parasitic capacitance (PC) descriptions thereof, searching the database for one amongst the predefined cells (matching predefined cell) that is a substantial match to the candidate cell: and, when a substantial match is found, assigning the PC description of the matching predefined cell to the candidate cell.

METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION (17719294)

Main Inventor

Kea Tiong TANG

Brief explanation

This abstract describes a method for training and updating a spiking neural network (SNN) in two different devices. The method involves training the SNN in the first device to generate multiple weight values. These weight values are then used to calculate a set of second weight values based on a threshold value and the number of bits used for the first weight values. The second weight values are then used to retrain the SNN and update the weights. Finally, the updated weight values are saved in a memory in the second device for performing SNN operations.

Abstract

A method is provided and includes operations as below: training a spiking neural network (SNN) in a first device to generate multiple first weight values of M bits; calculating multiple second weight values of N bits corresponding to the first weight values according to a threshold value, the number M, and the first weight values, wherein the number N is smaller than the number M; retraining the spiking neural network with the second weight values to update the second weight values; and performing a write operation to save the updated plurality of second weight values in a memory in a second device for performing a spiking neural network operation in the second device.

Low Power Scheme for Power Down in Integrated Dual Rail SRAMs (18328836)

Main Inventor

Sanjeev Kumar Jain

Brief explanation

The abstract describes a system and method for controlling the power down of a memory circuit. The system is designed to power down the input and logic components while keeping power to the memory cells. It includes two voltage rails, a clock generator, and a power detector. The power detector detects when the voltage on the input and logic components is below a certain threshold and generates a signal to disable the clock generator. This reduces dynamic power consumption by preventing unnecessary read/write cycles during power down.

Abstract

Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.

MEMORY DEVICE (18336428)

Main Inventor

He-Zhou WAN

Brief explanation

The abstract describes a memory device that consists of a memory array, a latch, and a logic element. The memory array operates based on a global write signal. The latch generates latch write data using a clock signal. The logic element generates the global write signal by combining the clock signal and the latch write data.

Abstract

A memory device includes a memory array, a first latch and a first logic element. The memory array is configured to operate according to a first global write signal. The first latch is configured to generate a first latch write data based on a clock signal. The first logic element is configured to generate the first global write signal based on the clock signal and the first latch write data.

MEMORY DEVICE FOR REDUCING ACTIVE POWER (18336418)

Main Inventor

Tsung-Hsien HUANG

Brief explanation

This abstract describes a memory device that consists of several components. The first memory cell receives a signal called the first word line signal. The first tracking cell is designed to imitate the behavior of the first memory cell. The tracking bit line is responsible for transmitting a signal called the tracking bit line signal to the first tracking cell. The second tracking cell adjusts the tracking bit line signal based on the first word line signal. The word line driver adjusts the first word line signal based on the tracking bit line signal and the distance between the second tracking cell and a common node on the tracking bit line.

Abstract

A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.

SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18336386)

Main Inventor

Peng-Chun Liou

Brief explanation

This abstract describes a semiconductor device that has three conductive structures. The first and second conductive structures are positioned vertically and spaced apart horizontally. The device also has multiple third conductive structures that are placed across the first and second conductive structures. The first and second conductive structures have different widths along the horizontal direction. The third conductive structures are designed to be given different voltages based on the varying widths of the first and second conductive structures.

Abstract

A semiconductor device comprises a first conductive structure extending along a vertical direction and a second conductive structure extending along the vertical direction. The second conductive structure is spaced apart from the first conductive structure along a lateral direction. The semiconductor device further comprises a plurality of third conductive structures each extending along the lateral direction. The plurality of third conductive structures are disposed across the first and second conductive structures. The first and second conductive structures each have a varying width along the lateral direction. The plurality of third conductive structures are configured to be applied with respective different voltages in accordance with the varying width of the first and second conductive structures.

MEMORY DEVICE AND OPERATION METHOD THEREOF (17715959)

Main Inventor

Jer-Fu Wang

Brief explanation

The abstract describes a memory device that consists of memory cells, each containing a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell stores complementary data at two storage nodes. The non-volatile memory cell replicates and retains the data from the SRAM cell before it loses power. After the power supply is restored, the replicated data is rewritten back to the SRAM cell.

Abstract

A memory device and an operation method thereof are provided. The memory device includes memory cells, each having a static random access memory (SRAM) cell and a non-volatile memory cell. The SRAM cell is configured to store complementary data at first and second storage nodes. The non-volatile memory cell is configured to replicate and retain the complementary data before the SRAM cell loses power supply, and to rewrite the replicated data to the first and second storage nodes of the SRAM cell after the power supply of the SRAM cell is restored.

Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning (18336304)

Main Inventor

Jhon Jhy Liaw

Brief explanation

The abstract describes a type of memory cell called Static Random Access Memory (SRAM) and its different components. The read-port of the SRAM cell consists of a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. The write-port of the SRAM cell includes a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. 

All of these transistors are gate-all-around (GAA) transistors, which is a specific type of transistor design. The R_PG transistor has a certain width, the R_PD transistor has a different width, the W_PG transistor has another width, the W_PD transistor has a fourth width, and the W_PU transistor has a fifth width.

It is mentioned that the first and fourth channel widths (referring to the R_PG and W_PD transistors) are smaller than the second channel width (referring to the R_PD transistor). Additionally, the third channel width (referring to the W_PG transistor) is greater than the fifth channel width (referring to the W_PU transistor).

Abstract

A read-port of a Static Random Access Memory (SRAM) cell includes a read-port pass-gate (R_PG) transistor and a read-port pull-down (R_PD) transistor. A write-port of the SRAM cell port includes at least a write-port pass-gate (W_PG) transistor, a write-port pull-down (W_PD) transistor, and a write-port pull-up (W_PU) transistor. The R_PG transistor, the R_PD transistor, the W_PG transistor, the W_PD transistor, and the W_PU transistor are gate-all-around (GAA) transistors. The R_PG transistor has a first channel width. The R_PD transistor has a second channel width. The W_PG transistor has a third channel width. The W_PD transistor has a fourth channel width. The W_PU transistor has a fifth channel width. The first channel width and the fourth channel width are each smaller than the second channel width. The third channel width is greater than the fifth channel width.

MEMORY DEVICE AND SYSTEM (17716609)

Main Inventor

Yu-Der CHIH

Brief explanation

This abstract describes a memory device that consists of different components. It includes two active areas, each with a different type of doping. There are also two gate structures, one between the two active areas, which is used to store a specific bit of information. Another doped structure is present between the first doped structure and the second active area. This second doped structure, along with the first doped structure, receives a signal from the gate structure that corresponds to the stored bit of information.

Abstract

A memory device includes a first active area, a first doped structure of a first doping type, a second active area, a first gate structure and a second doped structure of a second doping type different from the first doping type. The second active area is disposed between the first active area and the first doped structure. The first gate structure is disposed between the first active area and the second active area in a layout view, and configured to store a first bit with the first active area and the second active area. The second doped structure is coupled to the first gate structure and disposed between the first doped structure and the second active area. The second doped structure and the first doped structure are configured to receive a first signal corresponding to the first bit from the first gate structure.

BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY (18332058)

Main Inventor

Chang-Chih Huang

Brief explanation

The abstract describes an integrated chip that includes multiple layers of conductive interconnect structures. The first layer is located on top of a substrate, and a memory stack is placed on this layer. A second layer of conductive interconnect structures is positioned between the opposing sidewalls of the first layer. A third layer of conductive interconnect structures is placed on top of the first layer, with its top surface directly above the second layer.

Abstract

Various embodiments of the present application are directed towards an integrated chip including a first conductive interconnect structure overlying a substrate. A first memory stack is disposed on the first conductive interconnect structure. A second conductive interconnect structure overlies the first memory stack. The second conductive interconnect structure is spaced laterally between opposing sidewalls of the first conductive interconnect structure. A third conductive interconnect structure is disposed on the first conductive interconnect structure. A top surface of the third conductive interconnect structure is vertically above the second conductive interconnect structure.

MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY (17715964)

Main Inventor

Kerem Akarvardar

Brief explanation

The abstract describes a memory array and its components, including memory cells, floating gate transistors, bit lines, and word lines. The memory cells consist of a capacitor and an electrically programmable non-volatile memory (NVM) connected in series, along with a write transistor. The floating gate transistors are connected to the capacitors in a column of memory cells, while the bit lines are connected to the electrically programmable NVMs in a row of memory cells. The word lines are connected to the gate terminals of the write transistors in a row of memory cells.

Abstract

A memory array, a memory structure and an operation method of a memory array are provided. The memory array includes memory cells, floating gate transistors, bit lines and word lines. The memory cells each comprise a capacitor and an electrically programmable non-volatile memory (NVM) serially connected to the capacitor, and further comprise a write transistor with a first source/drain terminal coupled to a common node of the capacitor and the electrically programmable NVM. The floating gate transistors respectively have a gate terminal electrically floated and coupled to the capacitors of a column of the memory cells. The bit lines respectively coupled to the electrically programmable NVMs of a row of the memory cells. The word lines respectively coupled to gate terminals of the write transistors in a row of the memory cells.

SEMICONDUCTOR BURIED LAYER (18203849)

Main Inventor

Hung-Te Lin

Brief explanation

The abstract describes a method for manufacturing semiconductors. A mask is placed on a semiconductor layer or substrate, and the area underneath the mask is etched to create a cavity. The cavity is then lined to create a containment structure. The containment structure is filled with a base semiconductor material, and then the mask is removed. Finally, at least one semiconductor device is made on or inside the base semiconductor material in the containment structure.

Abstract

In a semiconductor manufacturing method, a mask is disposed on a semiconductor layer or semiconductor substrate. The semiconductor layer or semiconductor substrate is etched in an area delineated by the mask to form a cavity. With the mask disposed on the semiconductor layer or semiconductor substrate, the cavity is lined to form a containment structure. With the mask disposed on the semiconductor layer or semiconductor substrate, the containment structure is filled with a base semiconductor material. After filling the containment structure with the base semiconductor material, the mask is removed. At least one semiconductor device is fabricated in and/or on the base semiconductor material deposited in the containment structure.

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18333100)

Main Inventor

Yu-Chen CHANG

Brief explanation

This abstract describes a method for creating a semiconductor structure. The process involves several steps, including the formation of mandrels over a target layer. These mandrels are then cut off to create openings. A spacer layer is then formed over the remaining mandrels. Additional mandrels are formed between the first set of mandrels, and one of them is cut off to create another opening. The spacer layer is then etched, followed by the etching of the target layer.

Abstract

A method for forming a semiconductor structure includes forming first mandrels over a target layer. The method for forming a semiconductor structure also includes forming a first opening to cut off one of the first mandrels. The method for forming a semiconductor structure also includes forming a spacer layer over the first mandrels. The method for forming a semiconductor structure also includes forming second mandrels over the spacer layer and between the first mandrels. The method for forming a semiconductor structure also includes forming a second opening to cut off one of the second mandrels. The method for forming a semiconductor structure also includes etching the spacer layer. The method for forming a semiconductor structure also includes etching the target layer.

WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS (17894862)

Main Inventor

Ren-Hau Wu

Brief explanation

The abstract describes a cart designed for transporting wafers, which includes a separator and an airtight lock to ensure the wafer's safety. It also introduces a wafer transfer system that consists of a cart, a first workstation for loading and pressurizing the cart, and a second workstation for depressurizing and unloading the cart. The method for transporting wafers involves docking the cart, loading the wafer holder, pressurizing the space, maintaining the pressure, and moving the cart away from the workstation.

Abstract

A cart for wafer transportation includes a cart body, a separator disposed between first and second wafer holders, an airtight lock configured to seal the cart body. A wafer transfer system includes a cart including a space for holding a wafer holder, a first workstation configured to load the wafer holder into the space and pressurize the space, and a second workstation configured to depressurize the space and unload the wafer holder from the space, wherein the cart is transportable between the first workstation and the second workstation. A method for transporting wafers includes docking a cart in a workstation; loading a wafer holder into a space of the cart; pressurizing the space to cause a pressure of the space to be greater than an atmospheric pressure; maintaining the pressure of the space at the pressure; and moving the cart carrying the wafer holder away from the workstation.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17719040)

Main Inventor

Fan-Cheng LIN

Brief explanation

This method involves several steps to fabricate a semiconductor device. First, a semiconductor fin is formed on a substrate. Then, an isolation structure is created on the substrate. Next, a layer of metal oxide is deposited over the isolation structure, followed by a layer of oxide. Another layer of metal oxide is then deposited on top. These metal oxide layers have amorphous structures. A chemical mechanism polishing (CMP) process is performed to smooth out the metal oxide layers. After the CMP process, an annealing process is carried out to convert the amorphous structures of the metal oxide layers into crystalline structures. A gate structure is then formed over the semiconductor fin, and source/drain structures are formed on opposite sides of the gate structure.

Abstract

A method includes forming a semiconductor fin protruding over a substrate; forming an isolation structure over the substrate; depositing a first metal oxide layer over the isolation structure; depositing a first oxide layer over the first metal oxide layer; depositing a second metal oxide layer over the first oxide layer, in which the first metal oxide layer and the second metal oxide layer comprise amorphous structures; performing a chemical mechanism polishing (CMP) process to the first metal oxide layer, the first oxide layer, and the second metal oxide layer; after the CMP process is completed, performing an annealing process such that the first metal oxide layer and the second metal oxide layer are transferred from the amorphous structures into crystalline structures; forming a gate structure over the semiconductor fin; and forming source/drain structures over the substrate and on opposite sides of the gate structure.

SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT (18333124)

Main Inventor

Wen-Sheh HUANG

Brief explanation

The abstract describes a semiconductor device structure that consists of multiple layers. It includes a first dielectric layer and two conductive features surrounded by the first dielectric layer. There is also a second dielectric layer on top of the first dielectric layer, and a resistive element is connected to one of the conductive features. The second dielectric layer surrounds a part of the resistive element. Additionally, there is a conductive via connected to the other conductive feature, and the second dielectric layer surrounds a part of the via. The contact area between the resistive element and the first conductive feature is wider than the contact area between the via and the second conductive feature.

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first dielectric layer and a first conductive feature and a second conductive feature surrounded by the first dielectric layer. The semiconductor device structure also includes a second dielectric layer over the first dielectric layer and a resistive element electrically connected to the first conductive feature. The second dielectric layer surrounds a portion of the resistive element. The semiconductor device structure further includes a conductive via electrically connected to the second conductive feature. The second dielectric layer surrounds a portion of the conductive via, and a contact area between the resistive element and the first conductive feature is wider than a contact area between the conductive via and the second conductive feature.

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17715967)

Main Inventor

Chia-Cheng Chao

Brief explanation

The abstract describes a manufacturing method for a semiconductor device. The method involves creating a stack of alternating layers of different types of semiconductor materials. A patterned mask layer is then formed on the topmost layer of the stack. A trench is created in the stack using the patterned mask layer as a guide, resulting in the formation of a fin structure. A cladding layer is then applied along the sidewalls of the fin structure. The patterned mask layer and a portion of the cladding layer are removed using a two-step etching process. This removal results in the formation of cladding spacers with a concave top surface that gradually deepens from the sidewalls of the fin structure.

Abstract

A manufacturing method of a semiconductor device includes forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, where a topmost layer of the stack is one of the second semiconductor layers; forming a patterned mask layer on the topmost layer of the stack; forming a trench in the stack based on the patterned mask layer to form a fin structure; forming a cladding layer extending along sidewalls of the fin structure; and removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, where the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.

WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES (17815884)

Main Inventor

Shahaji B. More

Brief explanation

The abstract describes a new type of structure for multigate devices, specifically the source/drain structures. These structures have a wavy shape and are made using epitaxial growth. The device includes two fins that run parallel to each other, with each fin having a recessed and non-recessed portion. A gate is placed along a different direction and wraps around the non-recessed portions of the fins. The recessed portions of the fins are then merged together to form a single epitaxial source/drain. A contact is placed on top of this merged source/drain, and there is a V-shaped interface between the contact and the merged source/drain. The contact also extends below the tops of the non-recessed portions of the fins.

Abstract

Wavy-shaped epitaxial source/drain structures for multigate devices and methods of fabrication thereof are disclosed herein. An exemplary device includes a first fin and a second fin extending lengthwise along a first direction. The first fin and the second fin each have a non-recessed portion and a recessed portion. A gate extends lengthwise along a second direction that is different than the first direction. The gate wraps the non-recessed portion of the first fin and the non-recessed portion of the second fin. A merged epitaxial source/drain is on the recessed portion of the first fin and the recessed portion of the second fin. A source/drain contact is on the merged epitaxial source/drain. The source/drain contact and the merged epitaxial source/drain have a V-shaped interface therebetween. The source/drain contact extends below tops of the non-recessed portions of the first fin and the second fin.

SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF (18205538)

Main Inventor

Shahaji B. More

Brief explanation

The present disclosure describes methods for creating merged source/drain features by combining multiple fin structures. These merged features have a higher height percentage in a specific area, allowing for better connection with source/drain contact features and reducing resistance. Some embodiments also include voids within the merged portion.

Abstract

Embodiments of the present disclosure provide methods for forming merged source/drain features from two or more fin structures. The merged source/drain features according to the present disclosure have a merged portion with an increased height percentage over the overall height of the source/drain feature. The increase height percentage provides an increased landing range for source/drain contact features, therefore, reducing the connection resistance between the source/drain feature and the source/drain contact features. In some embodiments, the emerged source/drain features include one or more voids formed within the merged portion.

METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS (18335065)

Main Inventor

Chun-Hung Chen

Brief explanation

The abstract describes a type of field-effect transistor device that has a specific structure. It consists of a substrate with different doped regions and blocks, fins, insulators, and gate stacks. The substrate has two doped regions and blocks located above them. The doping concentrations of the blocks are lower than the doping concentrations of the corresponding regions. The fins are located above the blocks. Insulators are placed on the blocks and cover the fins. Dielectric strips are positioned between the fins and between the blocks. Finally, gate stacks are placed over the fins and above the insulators.

Abstract

A fin-type field-effect transistor device includes a substrate, insulators, gate stacks and dielectric strips. The substrate includes a first doped region, a second doped region, third doped blocks located above the first doped region and fourth doped blocks located above the second doped region, and fins located above the third doped blocks and the fourth doped blocks, wherein doping concentrations of the third doped blocks are lower than a doping concentration of the first doped region, and doping concentrations of the fourth doped blocks are lower than a doping concentration of the second doped region. The insulators are disposed on the third doped blocks and the fourth doped blocks of the substrate and covering the fins. The dielectric strips are disposed in between the fins, and in between the third doped blocks and the fourth doped blocks. The gate stacks are disposed over the fins and above the insulators.

DAISY-CHAIN SEAL RING STRUCTURE (18335413)

Main Inventor

Chun-Liang LU

Brief explanation

This abstract describes a semiconductor device that consists of two wafers. The device includes a seal ring structure, which is made up of three metal structures embedded in the bodies of the wafers. The first wafer has a first metal structure and a second metal structure, while the second wafer has a third metal structure. The device also includes a metal bonding structure that connects these metal structures. This bonding structure consists of a first set of metal elements that connect the first metal structure of the first wafer with the third metal structure of the second wafer, and a second set of metal elements that connect the second metal structure of the first wafer with the third metal structure of the second wafer.

Abstract

A semiconductor device includes a first wafer and a second wafer. The semiconductor device includes a seal ring structure comprising a first metal structure in a body of the first wafer, a second metal structure in the body of the first wafer, a third metal structure in a body of the second wafer, and a metal bonding structure including a first set of metal elements coupling the first metal structure and the third metal structure through an interface between the first wafer and the second wafer, and a second set of metal elements coupling the second metal structure and the third metal structure through the interface between the first wafer and the second wafer.

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18334381)

Main Inventor

Wensen Hung

Brief explanation

The abstract describes a semiconductor structure that consists of a circuit substrate, a semiconductor die, and a cover. The semiconductor die is placed on the circuit substrate, and the cover is placed over both the semiconductor die and the circuit substrate. The cover is made up of a lid portion and a support portion. The structure is held together by a first adhesive that bonds the support portion to the circuit substrate, and a second adhesive that bonds the support portion to the lid portion.

Abstract

A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME (18334136)

Main Inventor

Chih-Liang CHEN

Brief explanation

This abstract describes a semiconductor device that includes various components such as a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure and the source/drain structures are positioned parallel to the front-side surface of the substrate. The backside via, on the other hand, runs perpendicular to the gate structure and source/drain structures. The backside via has two portions - one aligned with the source/drain structures and the other aligned with the gate structure. The first portion of the backside via has a wider width along the direction of the gate structure compared to the second portion. The power rail is located on the backside surface of the substrate and is connected to the backside via.

Abstract

A semiconductor device includes a substrate, a gate structure, source/drain structures, a backside via, and a power rail. The gate structure extends along a first direction parallel with a front-side surface of the substrate. The backside via extends along a second direction parallel with the front-side surface of the substrate but perpendicular to the first direction, the backside via has a first portion aligned with one of the source/drain structures along the first direction and a second portion aligned with the gate structure along the first direction, the first portion of the backside via has a first width along the first direction, and the second portion of the backside via has a second width along the first direction, in which the first width is greater than the second width. The power rail is on a backside surface of the substrate and in contact with the backside via.

INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL (17716485)

Main Inventor

Meng-Pei LU

Brief explanation

The abstract describes a semiconductor device that consists of a substrate and an interconnect layer. The interconnect layer contains a structure made of a special material called a topological material. This topological material can be a topological insulator, a topological semimetal, or a combination of both. The abstract also mentions a method for manufacturing this semiconductor device.

Abstract

A semiconductor device includes a substrate and an interconnect layer disposed over the substrate. The interconnect layer includes an interconnect structure which includes a topological material. The topological material includes a topological insulator, a topological semimetal, or a combination thereof. A method for manufacturing the semiconductor device is also disclosed.

PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (18328913)

Main Inventor

Po-Chen LAI

Brief explanation

The abstract describes a package structure that consists of several components. Firstly, there is a semiconductor die that is bonded to a redistribution structure using first bonding elements. Secondly, there is a wall structure that is also bonded to the redistribution structure using second bonding elements. The wall structure is made up of multiple partitions arranged in a ring shape, but with gaps in between. The semiconductor die is placed within this ring. Lastly, there is a substrate that is bonded to the other side of the redistribution structure using third bonding elements. The substrate is also electrically connected to the semiconductor die.

Abstract

A package structure is provided. The package structure includes a semiconductor die bonding on a first surface of a redistribution structure through first bonding elements, and a wall structure bonding on the first surface of the redistribution structure through second bonding elements. The wall structure includes a plurality of partitions laterally arranged in a discontinuous ring, and the semiconductor die is located within the discontinuous ring. The package structure also includes a substrate on a second surface of the redistribution structure through third bonding elements and in electrical connection with the semiconductor die

TRANSMISSION LINE STRUCTURE FOR RF SIGNAL (17716050)

Main Inventor

Hsiu-Ying CHO

Brief explanation

The abstract describes the design of transmission line structures. These structures consist of two conductive lines that are formed on a semiconductor substrate and extend in a certain direction. The first transmission line is made up of a main line, as well as several sub-lines that extend towards the first and second conductive lines. Between the sub-lines and the conductive lines, there are zones of dielectric material. These dielectric material zones are separated from the conductive lines and the transmission line by an insulation material. The insulation material has a lower dielectric constant than the dielectric material zones.

Abstract

Transmission line structures are provided. The first and second conductive lines are formed in a metal layer over the semiconductor substrate and extend in a first direction. The first transmission line includes a first sub-line extending in the first direction, a plurality of second sub-lines extending toward the first conductive line, and a plurality of third sub-lines extending toward the second conductive line. The first dielectric material zones are formed between the second sub-lines and the first conductive line. The second dielectric material zones are formed between the third sub-lines and the second conductive line. The first and second dielectric material zones are separated from the first and second conductive lines and the first transmission line by an insulation material. Dielectric constant of the insulation material is less than that of the first and second dielectric material zones.

SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS (17714147)

Main Inventor

Jen-Yuan Chang

Brief explanation

The abstract describes a semiconductor package that includes an interposer, a stack of System on Integrated Chips (SoIC) bonded to the interposer, and multiple chips bonded to the interposer. The distance between the boundary of the SoIC die stack and the boundary of a neighboring chip is larger than a specific threshold distance in a particular direction.

Abstract

A semiconductor package is provided. The semiconductor package includes: an interposer; a System on Integrated Chips (SoIC) die stack bonded to a top surface of the interposer, the SoIC die stack comprising two or more dies bonded together; and a plurality of chips bonded to the top surface of the interposer. A first lateral distance, in a first direction, between a first boundary of the SoIC die stack and a boundary of a neighboring chip among the plurality of chips is larger than a first threshold distance.

3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS (17848815)

Main Inventor

Yao-Chung Chang

Brief explanation

The abstract describes a three-dimensional integrated circuit (3D IC) that is made up of two semiconductor chips. The first chip has a certain type of semiconductor material with a specific bandgap, and it also has a device built on it. The second chip has a different type of semiconductor material with a different bandgap, and it also has a device built on it. These two chips are stacked on top of each other and bonded together to create the 3D IC.

Abstract

Various embodiments of the present disclosure are directed towards a three-dimensional (3D) IC comprising semiconductor substrates with different bandgaps. The 3D IC chip comprises a first IC chip and a second IC chip overlying and bonded to the first IC chip. The first IC chip comprises a first semiconductor substrate with a first bandgap, and further comprises and a first device on and partially formed by the first semiconductor substrate. The second IC chip comprises a second semiconductor substrate with a second bandgap different than the first bandgap, and further comprises a second device on the second semiconductor substrate.

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18334390)

Main Inventor

Po-Yao Lin

Brief explanation

The abstract describes a package structure and a method of creating it. The structure consists of three tiers: the first tier has an interposer, the second tier has a bottom die, and the third tier has multiple first dies and at least one second die. The second die is positioned between the first dies. The first dies are connected to the bottom die through first connectors to create a signal path, and they are connected to the interposer through second connectors to create a power path. The first connectors are closer to the second die than the second connectors.

Abstract

Provided are a package structure and a method of forming the same. The package structure includes a first tier, a second tier, and a third tier. The first tier includes an interposer. The second tier is disposed on the first tier and includes a bottom die. The third tier is disposed on the second tier and includes a plurality of first dies and at least one second die. The at least one second die is disposed between the plurality of first dies. The plurality of first dies are electrically connected to the bottom die by a plurality of first connectors to form a signal path, the plurality of first dies are electrically connected to the interposer by a plurality of second connectors to form a power path, and the plurality of first connectors are closer to the at least one second die than the plurality of second connectors.

ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR (17861708)

Main Inventor

Cheng-Ying Ho

Brief explanation

The abstract describes a type of image sensor that includes a photodetector embedded in a semiconductor substrate. The sensor also has a dielectric structure on one side of the substrate, and an isolation structure that extends from the dielectric structure into the substrate. The isolation structure surrounds the photodetector and is made of a different material than the dielectric structure.

Abstract

Various embodiments of the present disclosure are directed towards an image sensor having a photodetector disposed within a semiconductor substrate. A dielectric structure is disposed on a first side of the semiconductor substrate. An isolation structure extends from the dielectric structure into the first side of the semiconductor substrate. The isolation structure laterally wraps around the photodetector and comprises an upper portion disposed above the first side of the semiconductor substrate and directly contacting sidewalls of the dielectric structure. The isolation structure comprises a first material different from a second material of the dielectric structure.

METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17658732)

Main Inventor

Yuan-Sheng HUANG

Brief explanation

This abstract describes techniques and apparatuses for creating a semiconductor device with a metal-insulator-metal capacitor. The capacitor includes a dielectric pad layer that is positioned between a bottom metal electrode layer and a portion of an insulator layer. The purpose of the dielectric pad layer is to maintain the thickness of the insulator layer, which helps to prevent leakage between the top and bottom metal electrode layers. Additionally, the dielectric pad layer allows for a reduction in the thickness of the insulator layer, which in turn increases the capacitance of the metal-insulator-metal capacitor.

Abstract

Some implementations described herein provide techniques and apparatuses for forming a semiconductor device including a metal-insulator-metal capacitor. The metal-insulator-metal capacitor includes a dielectric pad layer having a portion between a capacitor bottom metal electrode layer and a portion of an insulator layer. The dielectric pad layer may preserve a thickness of the insulator layer to reduce a likelihood of a leakage between a capacitor top metal electrode layer and the capacitor bottom metal electrode layer. The dielectric pad layer may also enable a reduction in a thickness of the insulator layer to increase a capacitance of the metal-insulator-metal capacitor.

CONTACT FIELD PLATE (17715900)

Main Inventor

Tao-Cheng Liu

Brief explanation

The abstract describes a semiconductor device and a method for creating it. The method involves placing two conductive structures on a semiconductor substrate and adding one or more dielectric layers between them. These dielectric layers are then covered with a masking layer. An opening is created in this masking layer, and a conductive material is deposited into the opening to create a field plate structure. Finally, this field plate structure is connected to another conductor.

Abstract

A semiconductor device and method of forming the semiconductor device are disclosed. The method includes forming first and second conductive structures on a semiconductor substrate, forming one or more dielectric layers between the first and second conductive structures, covering the one or more dielectric layers with a first masking layer, forming a first opening in the first masking layer, depositing a conductive material in the first opening to form a field plate structure, and electrically connecting the field plate structure to another conductor.

INNER SPACER FOR SEMICONDUCTOR DEVICE (17716192)

Main Inventor

Fu-Ting YEN

Brief explanation

The abstract describes a device that contains a semiconductor unit. This unit includes a first source/drain portion, a second source/drain portion, and at least one nanosheet segment that connects the first and second source/drain portions. The device also has a gate portion surrounding the nanosheet segment, as well as two inner spacer portions that separate the gate portion from the source/drain portions. These inner spacer portions have a carbon-rich region that faces the gate portion.

Abstract

A device includes at least one semiconductor unit which includes a first source/drain portion, a second source/drain portion, at least one nanosheet segment which is disposed to interconnect the first and second source/drain portions, a gate portion disposed around the at least one nanosheet segment, and a first inner spacer portion and a second inner spacer portion which are disposed to separate the gate portion from the first and second source/drain portions, respectively. Each of the first and second inner spacer portions has a carbon-rich region which confronts the gate portion.

BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME (18163649)

Main Inventor

Shahaji B. More

Brief explanation

This method involves creating a semiconductor fin that sticks out from a semiconductor substrate. The fin has two parts: an epitaxial portion and a mesa portion underneath it. The epitaxial portion consists of multiple channel layers and sacrificial layers. The semiconductor substrate has a top surface that is in a specific crystal plane. The method also includes creating a dummy gate structure that spans across the semiconductor fin. Then, the epitaxial portion of the fin adjacent to the dummy gate structure is removed to create a recess. A buffer semiconductor region is grown in this recess, followed by the growth of a source/drain feature on top of the buffer semiconductor region. Finally, the dummy gate structure is replaced with a metal gate structure. The buffer semiconductor region also has a top surface in the same crystal plane as the semiconductor substrate.

Abstract

A method includes forming a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin has an epitaxial portion and a mesa portion under the epitaxial portion. The epitaxial portion has a plurality of channel layers interleaved with a plurality of sacrificial layers. The semiconductor substrate has a top surface in (110) crystal plane. The method also includes forming a dummy gate structure across the semiconductor fin, removing at least the epitaxial portion of the semiconductor fin in a region adjacent the dummy gate structure to form a recess, epitaxially growing a buffer semiconductor region in the recess, epitaxially growing a source/drain feature on the buffer semiconductor region, and replacing the dummy gate structure with a metal gate structure. The buffer semiconductor region has a top surface in (110) crystal plane.

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17717892)

Main Inventor

Ta-Chun LIN

Brief explanation

This abstract describes a method for creating a semiconductor device structure. The method involves several steps, including forming a gate stack on a substrate, creating a spacer structure on the side of the gate stack, and forming a source/drain structure on the substrate. The spacer structure is positioned between the source/drain structure and the gate stack. The method also involves partially removing the outer layer and the middle layer, leaving behind lower portions of each layer between the source/drain structure and the gate stack.

Abstract

A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer structure over a sidewall of the gate stack. The method includes forming a source/drain structure in and over the substrate, wherein a portion of the spacer structure is between the source/drain structure and the gate stack. The method includes partially removing the outer layer, wherein a first lower portion of the outer layer remains between the source/drain structure and the gate stack. The method includes partially removing the middle layer, wherein a second lower portion of the middle layer remains between the source/drain structure and the gate stack.

METHOD OF FORMING SEMICONDUCTOR DEVICE (17714630)

Main Inventor

Chieh-Wei CHEN

Brief explanation

This abstract describes a method for creating a semiconductor device. The process involves creating a structure with source/drain regions, a fin, and a dummy gate. The dummy gate is then removed to create a gate trench. A gate dielectric layer and a work function structure are added to the trench. A resist layer is applied to fill the trench, and then the top portion of the resist layer is removed. The exposed work function structure is then removed using a wet chemical etchant. The resist layer is then removed, and a conductive gate is formed in the trench.

Abstract

A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME (18336044)

Main Inventor

Yu-Wei Jiang

Brief explanation

The abstract describes the structure of a transistor, which is an electronic device used to control the flow of electrical current. The transistor consists of several layers including a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line, and a bit line.

The ferroelectric layer is placed on top of the gate electrode, while the channel layer is placed on top of the ferroelectric layer. The gas impermeable layer is located between the channel layer and the gate electrode, and it is in contact with the ferroelectric layer. The dielectric layer surrounds both the ferroelectric layer and the channel layer, and it is in contact with the gas impermeable layer.

Embedded within the dielectric layer are the source line and the bit line, which are connected to the channel layer. These lines are responsible for providing the necessary electrical connections for the transistor to function properly.

Overall, this abstract provides a concise description of the different layers and components that make up the transistor structure.

Abstract

A transistor includes a gate electrode, a ferroelectric layer, a channel layer, a gas impermeable layer, a dielectric layer, a source line and a bit line. The ferroelectric layer is disposed on the gate electrode. The channel layer is disposed on the ferroelectric layer. The gas impermeable layer is disposed in between the channel layer and the gate electrode, and in contact with the ferroelectric layer. The dielectric layer is surrounding the ferroelectric layer and the channel layer, and in contact with the gas impermeable layer. The source line and the bit line are embedded in the dielectric layer and connected to the channel layer.

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (18333982)

Main Inventor

Shu-Jui CHANG

Brief explanation

This method involves creating a layer of a 2-D material on a substrate, which consists of transition metal atoms and chalcogen atoms. A gate structure is then formed on top of this layer. Chemical molecules are introduced to the 2-D material layer, causing certain atoms of the molecules to react with specific parts of the chalcogen atoms. This reaction weakens the covalent bonds between these parts of the chalcogen atoms and the transition metal atoms. Finally, source/drain contacts are formed on the 2-D material layer, where the contact metal atoms of these contacts create metallic bonds with the transition metal atoms of the 2-D material layer.

Abstract

A method includes forming a 2-D material layer over a substrate, wherein the 2-D material layer comprises transition metal atoms and chalcogen atoms; forming a gate structure over the 2-D material layer; supplying chemical molecules to the 2-D material layer, such that atoms of the chemical molecules react with portions of the chalcogen atoms to weaken covalent bonds between the portions of the chalcogen atoms and the transition metal atoms; and forming source/drain contacts over the 2-D material layer, wherein contact metal atoms of the source/drain contacts form metallic bonds with the transition metal atoms of the 2-D material layer.

FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING (18331241)

Main Inventor

Hung-Li Chiang

Brief explanation

The abstract describes a new type of transistor called MFMIS-FET, which has a three-dimensional structure that allows it to have a larger effective area than traditional transistors. This is achieved by combining the gate electrode of the transistor with the bottom electrode of the MFM (Metal Ferroelectric Metal) structure. In some cases, the areas of the gate electrode and bottom electrode are equal, while in others they are nearly equal. This design helps to reduce the capacitance ratio between the MFM structure and the transistor without decreasing the area of the MFM structure, which would otherwise reduce the drain current.

Abstract

An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.

ELECTROSTATIC DISCHARGE PROTECTION (17865809)

Main Inventor

Chia-Hui Chen

Brief explanation

The abstract describes a device that provides protection against electrostatic discharge (ESD). The device includes an ESD detector that detects ESD at a pad. It also includes P-type and N-type transistors connected in series, as well as a drive circuit that provides an output signal to the pad. The device further includes a first protection circuit operating in a power domain, which disables the P-type transistors in response to the detected ESD. Additionally, there is a second protection circuit operating in another power domain, which disables the N-type transistors in response to the detected ESD.

Abstract

Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.

Pulse Width Control Apparatus and Method (17836046)

Main Inventor

Yi-An Lai

Brief explanation

This abstract describes a system that generates a pulse width modulation (PWM) signal with a specific duty cycle. The system includes a square wave generator that delays an input square wave signal to produce multiple square wave signals. These square wave signals are then processed by a logic device, which performs a logic operation on two of the square wave signals. This operation results in the generation of the PWM signal, with its duty cycle determined by the two selected square wave signals.

Abstract

Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.

PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE (18336252)

Main Inventor

Tsu Ching Yang

Brief explanation

The abstract describes a memory device that consists of multiple layers arranged on a substrate. It includes a first memory cell with conductive lines and a channel layer. There are also barrier structures and protective liner layers to separate and protect different components of the device.

Abstract

A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17716517)

Main Inventor

Meng-Han LIN

Brief explanation

This abstract describes a semiconductor memory device that consists of metal lines and memory arrays. Each memory array includes two sets of thin film transistors (TFTs), a first switch transistor, and a second switch transistor. The TFTs in each set are connected to each other in parallel. The first switch transistor is connected in series to one of the TFTs in the first set and one of the metal lines in a pair. The second switch transistor is connected in series to one of the TFTs in the second set and the other metal line in the pair.

Abstract

A semiconductor memory device includes pairs of metal lines and memory arrays. Each of the memory arrays includes first and second sets of thin film transistors (TFTs), a first switch transistor, and a second switch transistor. The TFTs in the first and second sets are electrically connected to each other in parallel. The first switch transistor is electrically connected in series to one of the TFTs in the first set and one of the metal lines in a corresponding one of the pairs of the metal lines. The second switch transistor is electrically connected in series to one of the TFTs in the second set and the other one of the metal lines in the corresponding one of the pairs of the metal lines.

HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION (18334590)

Main Inventor

Tsu Ching Yang

Brief explanation

The abstract describes a method for creating a memory device. It involves creating stacks of word lines and insulating layers on a semiconductor substrate. A data storage layer and a channel layer are formed on the sidewalls of the word line stacks. An inner insulating layer is then created between the channel layer. An isolation cut process is performed to create an isolation opening, which is filled with an isolation structure made of a second dielectric material. Source/drain openings are formed by etching through the inner insulating layer, and source/drain contacts are created in these openings.

Abstract

In some embodiments, the present disclosure relates to a method for forming a memory device, including forming a plurality of word line stacks respectively including a plurality of word lines alternatingly stacked with a plurality of insulating layers over a semiconductor substrate, forming a data storage layer along opposing sidewalls of the word line stacks, forming a channel layer along opposing sidewalls of the data storage layer, forming an inner insulating layer between inner sidewalls of the channel layer and including a first dielectric material, performing an isolation cut process including a first etching process through the inner insulating layer and the channel layer to form an isolation opening, forming an isolation structure filling the isolation opening and including a second dielectric material, performing a second etching process through the inner insulating layer on opposing sides of the isolation structure to form source/drain openings, and forming source/drain contacts in the source/drain openings.

FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME (18336105)

Main Inventor

Chun-Chieh Lu

Brief explanation

The abstract describes a ferroelectric memory device that consists of multiple layers stacked on a substrate. These layers include conductive layers and dielectric layers arranged alternately. A channel layer passes through these layers. A ferroelectric layer is placed between the channel layer and the conductive and dielectric layers. Additionally, there are oxygen scavenging layers along the sides of the conductive layers, which act as a barrier between the ferroelectric layer and the conductive layers.

Abstract

The present disclosure, in some embodiments, relates to a ferroelectric memory device. The ferroelectric memory device includes a multi-layer stack disposed on a substrate. The multi-layer stack has a plurality of conductive layers and a plurality of dielectric layers stacked alternately. A channel layer penetrates through the plurality of conductive layers and the plurality of dielectric layers. A ferroelectric layer is disposed between the channel layer and both of the plurality of conductive layers and the plurality of dielectric layers. A plurality of oxygen scavenging layers are disposed along sidewalls of the plurality of conductive layer. The plurality of oxygen scavenging layers laterally separate the ferroelectric layer from the plurality of conductive layers.

MEMORY DEVICE AND FORMING METHOD THEREOF (17718071)

Main Inventor

Meng-Han LIN

Brief explanation

The abstract describes a memory device that consists of several components. These components include a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is located on top of a substrate, and the gate dielectric layer is positioned on the side of the word line. The semiconductor layer is then placed on the side of the gate dielectric layer. The source line is in contact with one region of the semiconductor layer's side, while the resistance-switchable element is in contact with another region of the semiconductor layer's side.

Abstract

A memory device comprises a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is over a substrate. The gate dielectric layer is on a sidewall of the word line. The semiconductor layer is on a sidewall of the gate dielectric layer. The source line is in contact with a first region of a sidewall of the semiconductor layer. The resistance-switchable element is in contact with a second region of the sidewall of the semiconductor layer.

CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY (18335167)

Main Inventor

Rainer Yen-Chieh Huang

Brief explanation

The abstract describes an integrated chip that has a gate electrode and a gate dielectric layer made of a ferroelectric material. There is also an active structure made of a semiconductor material, with a source contact and a drain contact arranged on top. A capping structure made of a first metal material is placed between the source and drain contacts and over the active structure.

Abstract

In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE (17705653)

Main Inventor

Harry-Hak-Lay Chuang

Brief explanation

The abstract describes a ferroelectric memory device that consists of three main components: a bottom electrode, a ferroelectric structure, and a top electrode. The bottom electrode is made of molybdenum, a type of metal.

Abstract

The present disclosure relates to a ferroelectric memory device that includes a bottom electrode, a ferroelectric structure overlying the bottom electrode, and a top electrode overlying the ferroelectric structure where the bottom electrode includes molybdenum.

MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18333498)

Main Inventor

Carlos H. Diaz

Brief explanation

This abstract describes a semiconductor device that includes a transistor and an interconnect structure. The transistor has a source region and a drain region. The interconnect structure is placed over the semiconductor substrate and consists of multiple interlayer dielectric layers, a first via, and a memory cell. The interlayer dielectric layers are located above the semiconductor substrate. The first via is embedded in at least two of the interlayer dielectric layers and is electrically connected to the drain region of the transistor. The memory cell is positioned over the same interlayer dielectric layers and is electrically connected to the first via.

Abstract

A semiconductor device including a semiconductor substrate and an interconnect structure is provided. The semiconductor substrate includes a transistor, wherein the transistor has a source region and a drain region. The interconnect structure is disposed over the semiconductor substrate, wherein the interconnect structure includes a plurality of interlayer dielectric layers, a first via and a memory cell. The plurality of interlayer dielectric layers are over the semiconductor substrate. The first via is embedded in at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the drain region of the transistor. The memory cell is disposed over the at least two interlayer dielectric layers among the plurality of interlayer dielectric layers and electrically connected with the first via.