US Patent Application 18328836. Low Power Scheme for Power Down in Integrated Dual Rail SRAMs simplified abstract

Low Power Scheme for Power Down in Integrated Dual Rail SRAMs

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Sanjeev Kumar Jain of Ottawa (CA)

Low Power Scheme for Power Down in Integrated Dual Rail SRAMs - A simplified explanation of the abstract

• This abstract for appeared for US patent application number 18328836 Titled 'Low Power Scheme for Power Down in Integrated Dual Rail SRAMs'

Simplified Explanation

The abstract describes a system and method for controlling the power down of a memory circuit. The system is designed to power down the input and logic components while keeping power to the memory cells. It includes two voltage rails, a clock generator, and a power detector. The power detector detects when the voltage on the input and logic components is below a certain threshold and generates a signal to disable the clock generator. This reduces dynamic power consumption by preventing unnecessary read/write cycles during power down.

Original Abstract Submitted

Systems and methods are provided for controlling power down of an integrated dual rail memory circuit. The power down system is configured to power down the power rail for input and logic components (VDD) while maintaining power to the power rail for the memory cells (VDDM). The power down system includes two voltage rails, a clock generator, and a power detector for detecting the power on VDD. The power detector generates an isolated power signal when voltage on VDD is below a voltage threshold. The isolated power signal is configured to disable the clock generator and thus reduce dynamic power as the read/write cycle is not triggered during power down.