US Patent Application 18331241. FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING simplified abstract
Contents
FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Hung-Li Chiang of Taipei City (TW)
Chih-Sheng Chang of Hsinchu (TW)
Tzu-Chiang Chen of Hsinchu City (TW)
FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18331241 Titled 'FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING'
Simplified Explanation
The abstract describes a new type of transistor called MFMIS-FET, which has a three-dimensional structure that allows it to have a larger effective area than traditional transistors. This is achieved by combining the gate electrode of the transistor with the bottom electrode of the MFM (Metal Ferroelectric Metal) structure. In some cases, the areas of the gate electrode and bottom electrode are equal, while in others they are nearly equal. This design helps to reduce the capacitance ratio between the MFM structure and the transistor without decreasing the area of the MFM structure, which would otherwise reduce the drain current.
Original Abstract Submitted
An MFMIS-FET includes a MOSFET having a three-dimensional structure that allows the MOSFET to have an effective area that is greater than the footprint of the MFM or the MOSFET. In some embodiment, the gate electrode of the MOSFET and the bottom electrode of the MFM are united. In some, they have equal areas. In some embodiments, the MFM and the MOSFET have nearly equal footprints. In some embodiments, the effective area of the MOSFET is much greater than the effective area of the MFM. These structures reduce the capacitance ratio between the MFM structure and the MOSFET without reducing the area of the MFM structure in a way that would decrease drain current.
