US Patent Application 18336252. PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE simplified abstract
Contents
PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Sheng-Chih Lai of Hsinchu County (TW)
Kuo-Chang Chiang of Hsinchu City (TW)
Hung-Chang Sun of Kaohsiung City (TW)
Chen-Jun Wu of Hsinchu City (TW)
Feng-Cheng Yang of Zhudong Township (TW)
Chung-Te Lin of Tainan City (TW)
PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18336252 Titled 'PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE'
Simplified Explanation
The abstract describes a memory device that consists of multiple layers arranged on a substrate. It includes a first memory cell with conductive lines and a channel layer. There are also barrier structures and protective liner layers to separate and protect different components of the device.
Original Abstract Submitted
A memory device includes a stack of gate electrode layers and interconnect layers arranged over a substrate. A first memory cell that is arranged over the substrate includes a first source/drain conductive lines and a second source/drain conductive line extending vertically through the stack of gate electrode layers. A channel layer and a memory layer are arranged on outer sidewalls of the first and second source/drain conductive lines. A first barrier structure is arranged between the first and second source/drain conductive lines. A first protective liner layer separates the first barrier structure from each of the first and second source/drain conductive lines. A second barrier structure is arranged on an opposite side of the first source/drain conductive line and is spaced apart from the first source/drain conductive line by a second protective liner layer.
