Difference between revisions of "Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 12th, 2023"

From WikiPatents
Jump to navigation Jump to search
(Creating a new page)
 
(10 intermediate revisions by the same user not shown)
Line 1: Line 1:
 +
'''Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023'''
 +
 +
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of device structures, materials, and fabrication processes. Here is a summary of the recent patents filed by TSMC:
 +
 +
- Patent 1: A semiconductor device that includes a transistor and an interconnect structure. The interconnect structure consists of multiple interlayer dielectric layers, a via, and a memory cell. The memory cell is connected to the via and positioned over the interlayer dielectric layers.
 +
 +
- Patent 2: A ferroelectric memory device that includes a bottom electrode, a ferroelectric structure, and a top electrode. The bottom electrode is made of molybdenum.
 +
 +
- Patent 3: An integrated chip that includes a gate electrode, a gate dielectric layer made of a ferroelectric material, an active structure made of a semiconductor material, and a capping structure made of a metal material.
 +
 +
- Patent 4: A memory device that includes a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is located on top of a substrate, and the resistance-switchable element is in contact with the semiconductor layer.
 +
 +
- Patent 5: A ferroelectric memory device that includes multiple layers stacked on a substrate. These layers include conductive and dielectric layers arranged alternately, with a ferroelectric layer placed between them. Oxygen scavenging layers act as a barrier between the ferroelectric layer and the conductive layers.
 +
 +
- Patent 6: A method for creating a memory device that involves forming stacks of word lines and insulating layers on a semiconductor substrate, creating a data storage layer and a channel layer on the sidewalls of the word line stacks, and forming source/drain contacts.
 +
 +
- Patent 7: A semiconductor memory device that includes metal lines and memory arrays. Each memory array includes two sets of thin film transistors (TFTs) connected in parallel, and switch transistors connected in series to the TFTs and metal lines.
 +
 +
- Patent 8: A memory device that includes multiple layers of gate electrodes and interconnects on a substrate. The device includes a first memory cell with source/drain conductive lines and a channel layer and memory layer on the sides of these lines.
 +
 +
- Patent 9: A system for generating a pulse width modulation (PWM) signal with a specific duty cycle. The system includes a square wave generator, a logic device, and multiple square wave signals.
 +
 +
- Patent 10: A device for electrostatic discharge (ESD) protection that includes an ESD detector, P-type and N-type transistors connected in series, a drive circuit, and protection circuits operating in different power domains.
 +
 +
Notable applications:
 +
 +
* Memory devices with improved performance and reliability.
 +
* Ferroelectric memory devices with enhanced electrode materials.
 +
* Integrated chips with ferroelectric gate dielectric layers.
 +
* Memory devices with resistance-switchable elements.
 +
* Memory devices with stacked layers and oxygen scavenging layers.
 +
* Methods for fabricating memory devices with improved process efficiency.
 +
* Semiconductor memory devices with parallel thin film transistors.
 +
* Memory devices with barrier structures for improved performance.
 +
* Systems for generating PWM signals with specific duty cycles.
 +
* ESD protection devices with improved circuitry and power domain control.
 +
 +
 +
 +
 
==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023==
 
==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023==
  
−
===APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)===
+
===APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION ([[US Patent Application 18334386. APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION simplified abstract|18334386]])===
 +
 
 +
 
 +
'''Main Inventor'''
  
−
'''Inventor'''
 
 
Feng-Wei Kuo
 
Feng-Wei Kuo
  
−
===PELLICLE FRAME WITH STRESS RELIEF TRENCHES (18335232)===
 
  
−
'''Inventor'''
+
===PELLICLE FRAME WITH STRESS RELIEF TRENCHES ([[US Patent Application 18335232. PELLICLE FRAME WITH STRESS RELIEF TRENCHES simplified abstract|18335232]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Kuo-Hao LEE
 
Kuo-Hao LEE
  
−
===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18208794)===
 
  
−
'''Inventor'''
+
===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18208794. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract|18208794]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Li-Po YANG
 
Li-Po YANG
  
−
===METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM (18326354)===
 
  
−
'''Inventor'''
+
===METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM ([[US Patent Application 18326354. METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM simplified abstract|18326354]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chi YANG
 
Chi YANG
  
−
===EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION (17717709)===
 
  
−
'''Inventor'''
+
===EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION ([[US Patent Application 17717709. EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION simplified abstract|17717709]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
I-Hsiung HUANG
 
I-Hsiung HUANG
  
−
===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME (18335505)===
 
  
−
'''Inventor'''
+
===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME ([[US Patent Application 18335505. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME simplified abstract|18335505]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Ke-Ying SU
 
Ke-Ying SU
  
−
===METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION (17719294)===
 
  
−
'''Inventor'''
+
===METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION ([[US Patent Application 17719294. METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION simplified abstract|17719294]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Kea Tiong TANG
 
Kea Tiong TANG
  
−
===Low Power Scheme for Power Down in Integrated Dual Rail SRAMs (18328836)===
 
  
−
'''Inventor'''
+
===Low Power Scheme for Power Down in Integrated Dual Rail SRAMs ([[US Patent Application 18328836. Low Power Scheme for Power Down in Integrated Dual Rail SRAMs simplified abstract|18328836]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Sanjeev Kumar Jain
 
Sanjeev Kumar Jain
  
−
===MEMORY DEVICE (18336428)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE ([[US Patent Application 18336428. MEMORY DEVICE simplified abstract|18336428]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
He-Zhou WAN
 
He-Zhou WAN
  
−
===MEMORY DEVICE FOR REDUCING ACTIVE POWER (18336418)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE FOR REDUCING ACTIVE POWER ([[US Patent Application 18336418. MEMORY DEVICE FOR REDUCING ACTIVE POWER simplified abstract|18336418]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Tsung-Hsien HUANG
 
Tsung-Hsien HUANG
  
−
===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18336386)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18336386. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18336386]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Peng-Chun Liou
 
Peng-Chun Liou
  
−
===MEMORY DEVICE AND OPERATION METHOD THEREOF (17715959)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE AND OPERATION METHOD THEREOF ([[US Patent Application 17715959. MEMORY DEVICE AND OPERATION METHOD THEREOF simplified abstract|17715959]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Jer-Fu Wang
 
Jer-Fu Wang
  
−
===Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning (18336304)===
 
  
−
'''Inventor'''
+
===Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning ([[US Patent Application 18336304. Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning simplified abstract|18336304]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Jhon Jhy Liaw
 
Jhon Jhy Liaw
  
−
===MEMORY DEVICE AND SYSTEM (17716609)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE AND SYSTEM ([[US Patent Application 17716609. MEMORY DEVICE AND SYSTEM simplified abstract|17716609]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yu-Der CHIH
 
Yu-Der CHIH
  
−
===BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY (18332058)===
 
  
−
'''Inventor'''
+
===BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY ([[US Patent Application 18332058. BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY simplified abstract|18332058]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chang-Chih Huang
 
Chang-Chih Huang
  
−
===MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY (17715964)===
 
  
−
'''Inventor'''
+
===MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY ([[US Patent Application 17715964. MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY simplified abstract|17715964]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Kerem Akarvardar
 
Kerem Akarvardar
  
−
===SEMICONDUCTOR BURIED LAYER (18203849)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR BURIED LAYER ([[US Patent Application 18203849. SEMICONDUCTOR BURIED LAYER simplified abstract|18203849]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Hung-Te Lin
 
Hung-Te Lin
  
−
===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18333100)===
 
  
−
'''Inventor'''
+
===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18333100. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract|18333100]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yu-Chen CHANG
 
Yu-Chen CHANG
  
−
===WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS (17894862)===
 
  
−
'''Inventor'''
+
===WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS ([[US Patent Application 17894862. WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS simplified abstract|17894862]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Ren-Hau Wu
 
Ren-Hau Wu
  
−
===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17719040)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17719040. SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME simplified abstract|17719040]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Fan-Cheng LIN
 
Fan-Cheng LIN
  
−
===SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT (18333124)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT ([[US Patent Application 18333124. SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT simplified abstract|18333124]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Wen-Sheh HUANG
 
Wen-Sheh HUANG
  
−
===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17715967)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17715967. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17715967]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chia-Cheng Chao
 
Chia-Cheng Chao
  
−
===WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES (17815884)===
 
  
−
'''Inventor'''
+
===WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES ([[US Patent Application 17815884. WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES simplified abstract|17815884]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Shahaji B. More
 
Shahaji B. More
  
−
===SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF (18205538)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF ([[US Patent Application 18205538. SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF simplified abstract|18205538]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Shahaji B. More
 
Shahaji B. More
  
−
===METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS (18335065)===
 
  
−
'''Inventor'''
+
===METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS ([[US Patent Application 18335065. METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS simplified abstract|18335065]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chun-Hung Chen
 
Chun-Hung Chen
  
−
===DAISY-CHAIN SEAL RING STRUCTURE (18335413)===
 
  
−
'''Inventor'''
+
===DAISY-CHAIN SEAL RING STRUCTURE ([[US Patent Application 18335413. DAISY-CHAIN SEAL RING STRUCTURE simplified abstract|18335413]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chun-Liang LU
 
Chun-Liang LU
  
−
===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18334381)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18334381. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract|18334381]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Wensen Hung
 
Wensen Hung
  
−
===INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME (18334136)===
 
  
−
'''Inventor'''
+
===INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME ([[US Patent Application 18334136. INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME simplified abstract|18334136]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chih-Liang CHEN
 
Chih-Liang CHEN
  
−
===INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL (17716485)===
 
  
−
'''Inventor'''
+
===INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL ([[US Patent Application 17716485. INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL simplified abstract|17716485]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Meng-Pei LU
 
Meng-Pei LU
  
−
===PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (18328913)===
 
  
−
'''Inventor'''
+
===PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 18328913. PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|18328913]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Po-Chen LAI
 
Po-Chen LAI
  
−
===TRANSMISSION LINE STRUCTURE FOR RF SIGNAL (17716050)===
 
  
−
'''Inventor'''
+
===TRANSMISSION LINE STRUCTURE FOR RF SIGNAL ([[US Patent Application 17716050. TRANSMISSION LINE STRUCTURE FOR RF SIGNAL simplified abstract|17716050]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Hsiu-Ying CHO
 
Hsiu-Ying CHO
  
−
===SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS (17714147)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS ([[US Patent Application 17714147. SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS simplified abstract|17714147]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Jen-Yuan Chang
 
Jen-Yuan Chang
  
−
===3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS (17848815)===
 
  
−
'''Inventor'''
+
===3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS ([[US Patent Application 17848815. 3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS simplified abstract|17848815]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yao-Chung Chang
 
Yao-Chung Chang
  
−
===PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18334390)===
 
  
−
'''Inventor'''
+
===PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME ([[US Patent Application 18334390. PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME simplified abstract|18334390]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Po-Yao Lin
 
Po-Yao Lin
  
−
===ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR (17861708)===
 
  
−
'''Inventor'''
+
===ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR ([[US Patent Application 17861708. ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR simplified abstract|17861708]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Cheng-Ying Ho
 
Cheng-Ying Ho
  
−
===METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17658732)===
 
  
−
'''Inventor'''
+
===METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING ([[US Patent Application 17658732. METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING simplified abstract|17658732]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yuan-Sheng HUANG
 
Yuan-Sheng HUANG
  
−
===CONTACT FIELD PLATE (17715900)===
 
  
−
'''Inventor'''
+
===CONTACT FIELD PLATE ([[US Patent Application 17715900. CONTACT FIELD PLATE simplified abstract|17715900]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Tao-Cheng Liu
 
Tao-Cheng Liu
  
−
===INNER SPACER FOR SEMICONDUCTOR DEVICE (17716192)===
 
  
−
'''Inventor'''
+
===INNER SPACER FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17716192. INNER SPACER FOR SEMICONDUCTOR DEVICE simplified abstract|17716192]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Fu-Ting YEN
 
Fu-Ting YEN
  
−
===BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME (18163649)===
 
  
−
'''Inventor'''
+
===BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME ([[US Patent Application 18163649. BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME simplified abstract|18163649]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Shahaji B. More
 
Shahaji B. More
  
−
===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17717892)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17717892. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17717892]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Ta-Chun LIN
 
Ta-Chun LIN
  
−
===METHOD OF FORMING SEMICONDUCTOR DEVICE (17714630)===
 
  
−
'''Inventor'''
+
===METHOD OF FORMING SEMICONDUCTOR DEVICE ([[US Patent Application 17714630. METHOD OF FORMING SEMICONDUCTOR DEVICE simplified abstract|17714630]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chieh-Wei CHEN
 
Chieh-Wei CHEN
  
−
===INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME (18336044)===
 
  
−
'''Inventor'''
+
===INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18336044. INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME simplified abstract|18336044]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yu-Wei Jiang
 
Yu-Wei Jiang
  
−
===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (18333982)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 18333982. SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME simplified abstract|18333982]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Shu-Jui CHANG
 
Shu-Jui CHANG
  
−
===FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING (18331241)===
 
  
−
'''Inventor'''
+
===FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING ([[US Patent Application 18331241. FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING simplified abstract|18331241]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Hung-Li Chiang
 
Hung-Li Chiang
  
−
===ELECTROSTATIC DISCHARGE PROTECTION (17865809)===
 
  
−
'''Inventor'''
+
===ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17865809. ELECTROSTATIC DISCHARGE PROTECTION simplified abstract|17865809]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chia-Hui Chen
 
Chia-Hui Chen
  
−
===Pulse Width Control Apparatus and Method (17836046)===
 
  
−
'''Inventor'''
+
===Pulse Width Control Apparatus and Method ([[US Patent Application 17836046. Pulse Width Control Apparatus and Method simplified abstract|17836046]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Yi-An Lai
 
Yi-An Lai
  
−
===PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE (18336252)===
 
  
−
'''Inventor'''
+
===PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE ([[US Patent Application 18336252. PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE simplified abstract|18336252]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Tsu Ching Yang
 
Tsu Ching Yang
  
−
===SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17716517)===
 
  
−
'''Inventor'''
+
===SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17716517. SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract|17716517]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Meng-Han LIN
 
Meng-Han LIN
  
−
===HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION (18334590)===
 
  
−
'''Inventor'''
+
===HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION ([[US Patent Application 18334590. HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION simplified abstract|18334590]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Tsu Ching Yang
 
Tsu Ching Yang
  
−
===FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME (18336105)===
 
  
−
'''Inventor'''
+
===FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18336105. FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract|18336105]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Chun-Chieh Lu
 
Chun-Chieh Lu
  
−
===MEMORY DEVICE AND FORMING METHOD THEREOF (17718071)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE AND FORMING METHOD THEREOF ([[US Patent Application 17718071. MEMORY DEVICE AND FORMING METHOD THEREOF simplified abstract|17718071]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Meng-Han LIN
 
Meng-Han LIN
  
−
===CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY (18335167)===
 
  
−
'''Inventor'''
+
===CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY ([[US Patent Application 18335167. CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY simplified abstract|18335167]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Rainer Yen-Chieh Huang
 
Rainer Yen-Chieh Huang
  
−
===MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE (17705653)===
 
  
−
'''Inventor'''
+
===MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE ([[US Patent Application 17705653. MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE simplified abstract|17705653]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Harry-Hak-Lay Chuang
 
Harry-Hak-Lay Chuang
  
−
===MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18333498)===
 
  
−
'''Inventor'''
+
===MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE ([[US Patent Application 18333498. MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE simplified abstract|18333498]])===
 +
 
 +
 
 +
'''Main Inventor'''
 +
 
 
Carlos H. Diaz
 
Carlos H. Diaz

Latest revision as of 10:29, 19 October 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023

Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of device structures, materials, and fabrication processes. Here is a summary of the recent patents filed by TSMC:

- Patent 1: A semiconductor device that includes a transistor and an interconnect structure. The interconnect structure consists of multiple interlayer dielectric layers, a via, and a memory cell. The memory cell is connected to the via and positioned over the interlayer dielectric layers.

- Patent 2: A ferroelectric memory device that includes a bottom electrode, a ferroelectric structure, and a top electrode. The bottom electrode is made of molybdenum.

- Patent 3: An integrated chip that includes a gate electrode, a gate dielectric layer made of a ferroelectric material, an active structure made of a semiconductor material, and a capping structure made of a metal material.

- Patent 4: A memory device that includes a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is located on top of a substrate, and the resistance-switchable element is in contact with the semiconductor layer.

- Patent 5: A ferroelectric memory device that includes multiple layers stacked on a substrate. These layers include conductive and dielectric layers arranged alternately, with a ferroelectric layer placed between them. Oxygen scavenging layers act as a barrier between the ferroelectric layer and the conductive layers.

- Patent 6: A method for creating a memory device that involves forming stacks of word lines and insulating layers on a semiconductor substrate, creating a data storage layer and a channel layer on the sidewalls of the word line stacks, and forming source/drain contacts.

- Patent 7: A semiconductor memory device that includes metal lines and memory arrays. Each memory array includes two sets of thin film transistors (TFTs) connected in parallel, and switch transistors connected in series to the TFTs and metal lines.

- Patent 8: A memory device that includes multiple layers of gate electrodes and interconnects on a substrate. The device includes a first memory cell with source/drain conductive lines and a channel layer and memory layer on the sides of these lines.

- Patent 9: A system for generating a pulse width modulation (PWM) signal with a specific duty cycle. The system includes a square wave generator, a logic device, and multiple square wave signals.

- Patent 10: A device for electrostatic discharge (ESD) protection that includes an ESD detector, P-type and N-type transistors connected in series, a drive circuit, and protection circuits operating in different power domains.

Notable applications:

  • Memory devices with improved performance and reliability.
  • Ferroelectric memory devices with enhanced electrode materials.
  • Integrated chips with ferroelectric gate dielectric layers.
  • Memory devices with resistance-switchable elements.
  • Memory devices with stacked layers and oxygen scavenging layers.
  • Methods for fabricating memory devices with improved process efficiency.
  • Semiconductor memory devices with parallel thin film transistors.
  • Memory devices with barrier structures for improved performance.
  • Systems for generating PWM signals with specific duty cycles.
  • ESD protection devices with improved circuitry and power domain control.



Contents

Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023

APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)

Main Inventor

Feng-Wei Kuo


PELLICLE FRAME WITH STRESS RELIEF TRENCHES (18335232)

Main Inventor

Kuo-Hao LEE


PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18208794)

Main Inventor

Li-Po YANG


METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM (18326354)

Main Inventor

Chi YANG


EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION (17717709)

Main Inventor

I-Hsiung HUANG


METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME (18335505)

Main Inventor

Ke-Ying SU


METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION (17719294)

Main Inventor

Kea Tiong TANG


Low Power Scheme for Power Down in Integrated Dual Rail SRAMs (18328836)

Main Inventor

Sanjeev Kumar Jain


MEMORY DEVICE (18336428)

Main Inventor

He-Zhou WAN


MEMORY DEVICE FOR REDUCING ACTIVE POWER (18336418)

Main Inventor

Tsung-Hsien HUANG


SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18336386)

Main Inventor

Peng-Chun Liou


MEMORY DEVICE AND OPERATION METHOD THEREOF (17715959)

Main Inventor

Jer-Fu Wang


Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning (18336304)

Main Inventor

Jhon Jhy Liaw


MEMORY DEVICE AND SYSTEM (17716609)

Main Inventor

Yu-Der CHIH


BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY (18332058)

Main Inventor

Chang-Chih Huang


MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY (17715964)

Main Inventor

Kerem Akarvardar


SEMICONDUCTOR BURIED LAYER (18203849)

Main Inventor

Hung-Te Lin


METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18333100)

Main Inventor

Yu-Chen CHANG


WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS (17894862)

Main Inventor

Ren-Hau Wu


SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17719040)

Main Inventor

Fan-Cheng LIN


SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT (18333124)

Main Inventor

Wen-Sheh HUANG


SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17715967)

Main Inventor

Chia-Cheng Chao


WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES (17815884)

Main Inventor

Shahaji B. More


SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF (18205538)

Main Inventor

Shahaji B. More


METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS (18335065)

Main Inventor

Chun-Hung Chen


DAISY-CHAIN SEAL RING STRUCTURE (18335413)

Main Inventor

Chun-Liang LU


SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18334381)

Main Inventor

Wensen Hung


INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME (18334136)

Main Inventor

Chih-Liang CHEN


INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL (17716485)

Main Inventor

Meng-Pei LU


PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (18328913)

Main Inventor

Po-Chen LAI


TRANSMISSION LINE STRUCTURE FOR RF SIGNAL (17716050)

Main Inventor

Hsiu-Ying CHO


SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS (17714147)

Main Inventor

Jen-Yuan Chang


3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS (17848815)

Main Inventor

Yao-Chung Chang


PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18334390)

Main Inventor

Po-Yao Lin


ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR (17861708)

Main Inventor

Cheng-Ying Ho


METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17658732)

Main Inventor

Yuan-Sheng HUANG


CONTACT FIELD PLATE (17715900)

Main Inventor

Tao-Cheng Liu


INNER SPACER FOR SEMICONDUCTOR DEVICE (17716192)

Main Inventor

Fu-Ting YEN


BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME (18163649)

Main Inventor

Shahaji B. More


SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17717892)

Main Inventor

Ta-Chun LIN


METHOD OF FORMING SEMICONDUCTOR DEVICE (17714630)

Main Inventor

Chieh-Wei CHEN


INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME (18336044)

Main Inventor

Yu-Wei Jiang


SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (18333982)

Main Inventor

Shu-Jui CHANG


FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING (18331241)

Main Inventor

Hung-Li Chiang


ELECTROSTATIC DISCHARGE PROTECTION (17865809)

Main Inventor

Chia-Hui Chen


Pulse Width Control Apparatus and Method (17836046)

Main Inventor

Yi-An Lai


PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE (18336252)

Main Inventor

Tsu Ching Yang


SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17716517)

Main Inventor

Meng-Han LIN


HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION (18334590)

Main Inventor

Tsu Ching Yang


FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME (18336105)

Main Inventor

Chun-Chieh Lu


MEMORY DEVICE AND FORMING METHOD THEREOF (17718071)

Main Inventor

Meng-Han LIN


CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY (18335167)

Main Inventor

Rainer Yen-Chieh Huang


MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE (17705653)

Main Inventor

Harry-Hak-Lay Chuang


MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18333498)

Main Inventor

Carlos H. Diaz

Retrieved from "http://wikipatents.org/index.php?title=Taiwan_Semiconductor_Manufacturing_Company,_Ltd._patent_applications_published_on_October_12th,_2023&oldid=3425"