Difference between revisions of "Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on October 12th, 2023"
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==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023== | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023== | ||
− | ===APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)=== | + | ===APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION ([[US Patent Application 18334386. APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION simplified abstract|18334386]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
− | |||
Feng-Wei Kuo | Feng-Wei Kuo | ||
− | |||
− | '''Inventor''' | + | ===PELLICLE FRAME WITH STRESS RELIEF TRENCHES ([[US Patent Application 18335232. PELLICLE FRAME WITH STRESS RELIEF TRENCHES simplified abstract|18335232]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Kuo-Hao LEE | Kuo-Hao LEE | ||
− | |||
− | '''Inventor''' | + | ===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18208794. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract|18208794]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Li-Po YANG | Li-Po YANG | ||
− | |||
− | '''Inventor''' | + | ===METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM ([[US Patent Application 18326354. METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM simplified abstract|18326354]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chi YANG | Chi YANG | ||
− | |||
− | '''Inventor''' | + | ===EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION ([[US Patent Application 17717709. EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION simplified abstract|17717709]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
I-Hsiung HUANG | I-Hsiung HUANG | ||
− | |||
− | '''Inventor''' | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME ([[US Patent Application 18335505. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME simplified abstract|18335505]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Ke-Ying SU | Ke-Ying SU | ||
− | |||
− | '''Inventor''' | + | ===METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION ([[US Patent Application 17719294. METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION simplified abstract|17719294]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Kea Tiong TANG | Kea Tiong TANG | ||
− | |||
− | '''Inventor''' | + | ===Low Power Scheme for Power Down in Integrated Dual Rail SRAMs ([[US Patent Application 18328836. Low Power Scheme for Power Down in Integrated Dual Rail SRAMs simplified abstract|18328836]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Sanjeev Kumar Jain | Sanjeev Kumar Jain | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE ([[US Patent Application 18336428. MEMORY DEVICE simplified abstract|18336428]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
He-Zhou WAN | He-Zhou WAN | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE FOR REDUCING ACTIVE POWER ([[US Patent Application 18336418. MEMORY DEVICE FOR REDUCING ACTIVE POWER simplified abstract|18336418]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Tsung-Hsien HUANG | Tsung-Hsien HUANG | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18336386. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract|18336386]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Peng-Chun Liou | Peng-Chun Liou | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE AND OPERATION METHOD THEREOF ([[US Patent Application 17715959. MEMORY DEVICE AND OPERATION METHOD THEREOF simplified abstract|17715959]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Jer-Fu Wang | Jer-Fu Wang | ||
− | |||
− | '''Inventor''' | + | ===Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning ([[US Patent Application 18336304. Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning simplified abstract|18336304]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Jhon Jhy Liaw | Jhon Jhy Liaw | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE AND SYSTEM ([[US Patent Application 17716609. MEMORY DEVICE AND SYSTEM simplified abstract|17716609]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yu-Der CHIH | Yu-Der CHIH | ||
− | |||
− | '''Inventor''' | + | ===BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY ([[US Patent Application 18332058. BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY simplified abstract|18332058]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chang-Chih Huang | Chang-Chih Huang | ||
− | |||
− | '''Inventor''' | + | ===MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY ([[US Patent Application 17715964. MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY simplified abstract|17715964]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Kerem Akarvardar | Kerem Akarvardar | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR BURIED LAYER ([[US Patent Application 18203849. SEMICONDUCTOR BURIED LAYER simplified abstract|18203849]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Hung-Te Lin | Hung-Te Lin | ||
− | |||
− | '''Inventor''' | + | ===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18333100. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract|18333100]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yu-Chen CHANG | Yu-Chen CHANG | ||
− | |||
− | '''Inventor''' | + | ===WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS ([[US Patent Application 17894862. WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS simplified abstract|17894862]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Ren-Hau Wu | Ren-Hau Wu | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17719040. SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME simplified abstract|17719040]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Fan-Cheng LIN | Fan-Cheng LIN | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT ([[US Patent Application 18333124. SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT simplified abstract|18333124]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Wen-Sheh HUANG | Wen-Sheh HUANG | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17715967. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract|17715967]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chia-Cheng Chao | Chia-Cheng Chao | ||
− | |||
− | '''Inventor''' | + | ===WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES ([[US Patent Application 17815884. WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES simplified abstract|17815884]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Shahaji B. More | Shahaji B. More | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF ([[US Patent Application 18205538. SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF simplified abstract|18205538]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Shahaji B. More | Shahaji B. More | ||
− | |||
− | '''Inventor''' | + | ===METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS ([[US Patent Application 18335065. METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS simplified abstract|18335065]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chun-Hung Chen | Chun-Hung Chen | ||
− | |||
− | '''Inventor''' | + | ===DAISY-CHAIN SEAL RING STRUCTURE ([[US Patent Application 18335413. DAISY-CHAIN SEAL RING STRUCTURE simplified abstract|18335413]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chun-Liang LU | Chun-Liang LU | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18334381. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract|18334381]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Wensen Hung | Wensen Hung | ||
− | |||
− | '''Inventor''' | + | ===INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME ([[US Patent Application 18334136. INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME simplified abstract|18334136]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chih-Liang CHEN | Chih-Liang CHEN | ||
− | |||
− | '''Inventor''' | + | ===INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL ([[US Patent Application 17716485. INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL simplified abstract|17716485]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Meng-Pei LU | Meng-Pei LU | ||
− | |||
− | '''Inventor''' | + | ===PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 18328913. PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|18328913]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Po-Chen LAI | Po-Chen LAI | ||
− | |||
− | '''Inventor''' | + | ===TRANSMISSION LINE STRUCTURE FOR RF SIGNAL ([[US Patent Application 17716050. TRANSMISSION LINE STRUCTURE FOR RF SIGNAL simplified abstract|17716050]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Hsiu-Ying CHO | Hsiu-Ying CHO | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS ([[US Patent Application 17714147. SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS simplified abstract|17714147]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Jen-Yuan Chang | Jen-Yuan Chang | ||
− | |||
− | '''Inventor''' | + | ===3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS ([[US Patent Application 17848815. 3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS simplified abstract|17848815]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yao-Chung Chang | Yao-Chung Chang | ||
− | |||
− | '''Inventor''' | + | ===PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME ([[US Patent Application 18334390. PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME simplified abstract|18334390]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Po-Yao Lin | Po-Yao Lin | ||
− | |||
− | '''Inventor''' | + | ===ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR ([[US Patent Application 17861708. ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR simplified abstract|17861708]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Cheng-Ying Ho | Cheng-Ying Ho | ||
− | |||
− | '''Inventor''' | + | ===METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING ([[US Patent Application 17658732. METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING simplified abstract|17658732]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yuan-Sheng HUANG | Yuan-Sheng HUANG | ||
− | |||
− | '''Inventor''' | + | ===CONTACT FIELD PLATE ([[US Patent Application 17715900. CONTACT FIELD PLATE simplified abstract|17715900]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Tao-Cheng Liu | Tao-Cheng Liu | ||
− | |||
− | '''Inventor''' | + | ===INNER SPACER FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17716192. INNER SPACER FOR SEMICONDUCTOR DEVICE simplified abstract|17716192]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Fu-Ting YEN | Fu-Ting YEN | ||
− | |||
− | '''Inventor''' | + | ===BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME ([[US Patent Application 18163649. BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME simplified abstract|18163649]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Shahaji B. More | Shahaji B. More | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17717892. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract|17717892]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Ta-Chun LIN | Ta-Chun LIN | ||
− | |||
− | '''Inventor''' | + | ===METHOD OF FORMING SEMICONDUCTOR DEVICE ([[US Patent Application 17714630. METHOD OF FORMING SEMICONDUCTOR DEVICE simplified abstract|17714630]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chieh-Wei CHEN | Chieh-Wei CHEN | ||
− | |||
− | '''Inventor''' | + | ===INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18336044. INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME simplified abstract|18336044]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yu-Wei Jiang | Yu-Wei Jiang | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME ([[US Patent Application 18333982. SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME simplified abstract|18333982]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Shu-Jui CHANG | Shu-Jui CHANG | ||
− | |||
− | '''Inventor''' | + | ===FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING ([[US Patent Application 18331241. FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING simplified abstract|18331241]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Hung-Li Chiang | Hung-Li Chiang | ||
− | |||
− | '''Inventor''' | + | ===ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17865809. ELECTROSTATIC DISCHARGE PROTECTION simplified abstract|17865809]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chia-Hui Chen | Chia-Hui Chen | ||
− | |||
− | '''Inventor''' | + | ===Pulse Width Control Apparatus and Method ([[US Patent Application 17836046. Pulse Width Control Apparatus and Method simplified abstract|17836046]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Yi-An Lai | Yi-An Lai | ||
− | |||
− | '''Inventor''' | + | ===PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE ([[US Patent Application 18336252. PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE simplified abstract|18336252]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Tsu Ching Yang | Tsu Ching Yang | ||
− | |||
− | '''Inventor''' | + | ===SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17716517. SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract|17716517]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Meng-Han LIN | Meng-Han LIN | ||
− | |||
− | '''Inventor''' | + | ===HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION ([[US Patent Application 18334590. HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION simplified abstract|18334590]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Tsu Ching Yang | Tsu Ching Yang | ||
− | |||
− | '''Inventor''' | + | ===FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18336105. FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract|18336105]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Chun-Chieh Lu | Chun-Chieh Lu | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE AND FORMING METHOD THEREOF ([[US Patent Application 17718071. MEMORY DEVICE AND FORMING METHOD THEREOF simplified abstract|17718071]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Meng-Han LIN | Meng-Han LIN | ||
− | |||
− | '''Inventor''' | + | ===CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY ([[US Patent Application 18335167. CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY simplified abstract|18335167]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Rainer Yen-Chieh Huang | Rainer Yen-Chieh Huang | ||
− | |||
− | '''Inventor''' | + | ===MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE ([[US Patent Application 17705653. MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE simplified abstract|17705653]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Harry-Hak-Lay Chuang | Harry-Hak-Lay Chuang | ||
− | |||
− | '''Inventor''' | + | ===MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE ([[US Patent Application 18333498. MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE simplified abstract|18333498]])=== |
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
Carlos H. Diaz | Carlos H. Diaz |
Latest revision as of 10:29, 19 October 2023
Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of device structures, materials, and fabrication processes. Here is a summary of the recent patents filed by TSMC:
- Patent 1: A semiconductor device that includes a transistor and an interconnect structure. The interconnect structure consists of multiple interlayer dielectric layers, a via, and a memory cell. The memory cell is connected to the via and positioned over the interlayer dielectric layers.
- Patent 2: A ferroelectric memory device that includes a bottom electrode, a ferroelectric structure, and a top electrode. The bottom electrode is made of molybdenum.
- Patent 3: An integrated chip that includes a gate electrode, a gate dielectric layer made of a ferroelectric material, an active structure made of a semiconductor material, and a capping structure made of a metal material.
- Patent 4: A memory device that includes a word line, a gate dielectric layer, a semiconductor layer, a source line, and a resistance-switchable element. The word line is located on top of a substrate, and the resistance-switchable element is in contact with the semiconductor layer.
- Patent 5: A ferroelectric memory device that includes multiple layers stacked on a substrate. These layers include conductive and dielectric layers arranged alternately, with a ferroelectric layer placed between them. Oxygen scavenging layers act as a barrier between the ferroelectric layer and the conductive layers.
- Patent 6: A method for creating a memory device that involves forming stacks of word lines and insulating layers on a semiconductor substrate, creating a data storage layer and a channel layer on the sidewalls of the word line stacks, and forming source/drain contacts.
- Patent 7: A semiconductor memory device that includes metal lines and memory arrays. Each memory array includes two sets of thin film transistors (TFTs) connected in parallel, and switch transistors connected in series to the TFTs and metal lines.
- Patent 8: A memory device that includes multiple layers of gate electrodes and interconnects on a substrate. The device includes a first memory cell with source/drain conductive lines and a channel layer and memory layer on the sides of these lines.
- Patent 9: A system for generating a pulse width modulation (PWM) signal with a specific duty cycle. The system includes a square wave generator, a logic device, and multiple square wave signals.
- Patent 10: A device for electrostatic discharge (ESD) protection that includes an ESD detector, P-type and N-type transistors connected in series, a drive circuit, and protection circuits operating in different power domains.
Notable applications:
- Memory devices with improved performance and reliability.
- Ferroelectric memory devices with enhanced electrode materials.
- Integrated chips with ferroelectric gate dielectric layers.
- Memory devices with resistance-switchable elements.
- Memory devices with stacked layers and oxygen scavenging layers.
- Methods for fabricating memory devices with improved process efficiency.
- Semiconductor memory devices with parallel thin film transistors.
- Memory devices with barrier structures for improved performance.
- Systems for generating PWM signals with specific duty cycles.
- ESD protection devices with improved circuitry and power domain control.
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023
- 1.1 APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)
- 1.2 PELLICLE FRAME WITH STRESS RELIEF TRENCHES (18335232)
- 1.3 PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18208794)
- 1.4 METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM (18326354)
- 1.5 EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION (17717709)
- 1.6 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME (18335505)
- 1.7 METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION (17719294)
- 1.8 Low Power Scheme for Power Down in Integrated Dual Rail SRAMs (18328836)
- 1.9 MEMORY DEVICE (18336428)
- 1.10 MEMORY DEVICE FOR REDUCING ACTIVE POWER (18336418)
- 1.11 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18336386)
- 1.12 MEMORY DEVICE AND OPERATION METHOD THEREOF (17715959)
- 1.13 Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning (18336304)
- 1.14 MEMORY DEVICE AND SYSTEM (17716609)
- 1.15 BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY (18332058)
- 1.16 MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY (17715964)
- 1.17 SEMICONDUCTOR BURIED LAYER (18203849)
- 1.18 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18333100)
- 1.19 WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS (17894862)
- 1.20 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17719040)
- 1.21 SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT (18333124)
- 1.22 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17715967)
- 1.23 WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES (17815884)
- 1.24 SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF (18205538)
- 1.25 METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS (18335065)
- 1.26 DAISY-CHAIN SEAL RING STRUCTURE (18335413)
- 1.27 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18334381)
- 1.28 INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME (18334136)
- 1.29 INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL (17716485)
- 1.30 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (18328913)
- 1.31 TRANSMISSION LINE STRUCTURE FOR RF SIGNAL (17716050)
- 1.32 SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS (17714147)
- 1.33 3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS (17848815)
- 1.34 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18334390)
- 1.35 ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR (17861708)
- 1.36 METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17658732)
- 1.37 CONTACT FIELD PLATE (17715900)
- 1.38 INNER SPACER FOR SEMICONDUCTOR DEVICE (17716192)
- 1.39 BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME (18163649)
- 1.40 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17717892)
- 1.41 METHOD OF FORMING SEMICONDUCTOR DEVICE (17714630)
- 1.42 INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME (18336044)
- 1.43 SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (18333982)
- 1.44 FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING (18331241)
- 1.45 ELECTROSTATIC DISCHARGE PROTECTION (17865809)
- 1.46 Pulse Width Control Apparatus and Method (17836046)
- 1.47 PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE (18336252)
- 1.48 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17716517)
- 1.49 HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION (18334590)
- 1.50 FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME (18336105)
- 1.51 MEMORY DEVICE AND FORMING METHOD THEREOF (17718071)
- 1.52 CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY (18335167)
- 1.53 MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE (17705653)
- 1.54 MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18333498)
Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on October 12th, 2023
APPARATUS FOR OPTICAL COUPLING AND SYSTEM FOR COMMUNICATION (18334386)
Main Inventor
Feng-Wei Kuo
PELLICLE FRAME WITH STRESS RELIEF TRENCHES (18335232)
Main Inventor
Kuo-Hao LEE
PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18208794)
Main Inventor
Li-Po YANG
METHOD FOR PERFORMING LITHOGRAPHY PROCESS, LIGHT SOURCE, AND EUV LITHOGRAPHY SYSTEM (18326354)
Main Inventor
Chi YANG
EUV LITHOGRAPHY APPARATUS AND OPERATING METHOD FOR MITIGATING CONTAMINATION (17717709)
Main Inventor
I-Hsiung HUANG
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SYSTEM FOR SAME (18335505)
Main Inventor
Ke-Ying SU
METHOD FOR NEURAL NETWORK WITH WEIGHT QUANTIZATION (17719294)
Main Inventor
Kea Tiong TANG
Low Power Scheme for Power Down in Integrated Dual Rail SRAMs (18328836)
Main Inventor
Sanjeev Kumar Jain
MEMORY DEVICE (18336428)
Main Inventor
He-Zhou WAN
MEMORY DEVICE FOR REDUCING ACTIVE POWER (18336418)
Main Inventor
Tsung-Hsien HUANG
SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18336386)
Main Inventor
Peng-Chun Liou
MEMORY DEVICE AND OPERATION METHOD THEREOF (17715959)
Main Inventor
Jer-Fu Wang
Sram Performance Optimization Via Transistor Width And Threshold Voltage Tuning (18336304)
Main Inventor
Jhon Jhy Liaw
MEMORY DEVICE AND SYSTEM (17716609)
Main Inventor
Yu-Der CHIH
BIT LINE AND WORD LINE CONNECTION FOR MEMORY ARRAY (18332058)
Main Inventor
Chang-Chih Huang
MEMORY ARRAY, MEMORY STRUCTURE AND OPERATION METHOD OF MEMORY ARRAY (17715964)
Main Inventor
Kerem Akarvardar
SEMICONDUCTOR BURIED LAYER (18203849)
Main Inventor
Hung-Te Lin
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (18333100)
Main Inventor
Yu-Chen CHANG
WAFER TRANSFER SYSTEM AND A METHOD FOR TRANSPORTING WAFERS (17894862)
Main Inventor
Ren-Hau Wu
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (17719040)
Main Inventor
Fan-Cheng LIN
SEMICONDUCTOR DEVICE STRUCTURE WITH RESISTIVE ELEMENT (18333124)
Main Inventor
Wen-Sheh HUANG
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17715967)
Main Inventor
Chia-Cheng Chao
WAVY-SHAPED EPITAXIAL SOURCE/DRAIN STRUCTURES (17815884)
Main Inventor
Shahaji B. More
SEMICONDUCTOR DEVICES HAVING MERGED SOURCE/DRAIN FEATURES AND METHODS OF FABRICATION THEREOF (18205538)
Main Inventor
Shahaji B. More
METHOD OF FABRICATING FIN-TYPE FIELD-EFFECT TRANSISTOR DEVICE HAVING SUBSTRATE WITH HEAVY DOPED AND LIGHT DOPED REGIONS (18335065)
Main Inventor
Chun-Hung Chen
DAISY-CHAIN SEAL RING STRUCTURE (18335413)
Main Inventor
Chun-Liang LU
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18334381)
Main Inventor
Wensen Hung
INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME (18334136)
Main Inventor
Chih-Liang CHEN
INTERCONNECT STRUCTURE INCLUDING TOPOLOGICAL MATERIAL (17716485)
Main Inventor
Meng-Pei LU
PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME (18328913)
Main Inventor
Po-Chen LAI
TRANSMISSION LINE STRUCTURE FOR RF SIGNAL (17716050)
Main Inventor
Hsiu-Ying CHO
SEMICONDUCTOR PACKAGE INCLUDING SOIC DIE STACKS (17714147)
Main Inventor
Jen-Yuan Chang
3D IC COMPRISING SEMICONDUCTOR SUBSTRATES WITH DIFFERENT BANDGAPS (17848815)
Main Inventor
Yao-Chung Chang
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18334390)
Main Inventor
Po-Yao Lin
ISOLATION STRUCTURE CONFIGURED TO REDUCE CROSS TALK IN IMAGE SENSOR (17861708)
Main Inventor
Cheng-Ying Ho
METAL-INSULATOR-METAL CAPACITOR AND METHODS OF MANUFACTURING (17658732)
Main Inventor
Yuan-Sheng HUANG
CONTACT FIELD PLATE (17715900)
Main Inventor
Tao-Cheng Liu
INNER SPACER FOR SEMICONDUCTOR DEVICE (17716192)
Main Inventor
Fu-Ting YEN
BUFFER EPITAXIAL REGION IN SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD OF THE SAME (18163649)
Main Inventor
Shahaji B. More
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME (17717892)
Main Inventor
Ta-Chun LIN
METHOD OF FORMING SEMICONDUCTOR DEVICE (17714630)
Main Inventor
Chieh-Wei CHEN
INTEGRATED CIRCUIT, TRANSISTOR AND METHOD OF FABRICATING THE SAME (18336044)
Main Inventor
Yu-Wei Jiang
SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME (18333982)
Main Inventor
Shu-Jui CHANG
FeFET OF 3D STRUCTURE FOR CAPACITANCE MATCHING (18331241)
Main Inventor
Hung-Li Chiang
ELECTROSTATIC DISCHARGE PROTECTION (17865809)
Main Inventor
Chia-Hui Chen
Pulse Width Control Apparatus and Method (17836046)
Main Inventor
Yi-An Lai
PROTECTIVE LINER LAYERS IN 3D MEMORY STRUCTURE (18336252)
Main Inventor
Tsu Ching Yang
SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME (17716517)
Main Inventor
Meng-Han LIN
HIGH SELECTIVITY ISOLATION STRUCTURE FOR IMPROVING EFFECTIVENESS OF 3D MEMORY FABRICATION (18334590)
Main Inventor
Tsu Ching Yang
FERROELECTRIC MEMORY DEVICE AND METHOD OF FORMING THE SAME (18336105)
Main Inventor
Chun-Chieh Lu
MEMORY DEVICE AND FORMING METHOD THEREOF (17718071)
Main Inventor
Meng-Han LIN
CAPPING LAYER OVER FET FERAM TO INCREASE CHARGE MOBILITY (18335167)
Main Inventor
Rainer Yen-Chieh Huang
MFM DEVICE WITH AN ENHANCED BOTTOM ELECTRODE (17705653)
Main Inventor
Harry-Hak-Lay Chuang
MEMORY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE (18333498)
Main Inventor
Carlos H. Diaz