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| − | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on December 28th, 2023==
| + | '''Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on December 28th, 2023''' |
| | | | |
| − | ===WET CLEANING TOOL AND METHOD ([[17847208. WET CLEANING TOOL AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847208]])===
| + | Taiwan Semiconductor Manufacturing Company, Ltd. has recently filed several patents related to various semiconductor devices and technologies. These patents cover a range of applications, including phase change devices, memory devices, and analog-to-digital converters. The company aims to address challenges in heat transfer, thermal management, memory storage, and data processing, while also improving device performance and reliability. |
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| | + | In terms of phase change devices, the company has developed a device with a substrate and a heater structure, along with a phase change element consisting of three connected portions. This device offers efficient heat transfer, improved thermal management, and enhanced cooling capabilities. It has potential applications in thermal management systems, heat transfer devices, and cooling systems. |
| | | | |
| − | '''Main Inventor'''
| + | For memory devices, the company has introduced innovative designs and materials to enhance performance and reliability. These memory devices include resistance variable storage devices, selectors, and ferroelectric or antiferroelectric layers. They offer higher data storage density, faster read and write speeds, lower power consumption, and improved durability. Potential applications include computer memory systems, data storage devices, solid-state drives (SSDs), and Internet of Things (IoT) devices. |
| | | | |
| − | Hsu. Tung. Yen
| + | In the field of analog-to-digital converters, the company has developed systems and methods to improve accuracy and noise cancellation capabilities. These ADCs consist of multiple quantization stages and noise cancellation filters, resulting in higher precision, reduced noise, and improved signal-to-noise ratio. They can be applied in high-precision measurement devices, audio and video recording equipment, and communication systems. |
| | | | |
| | + | Overall, Taiwan Semiconductor Manufacturing Company, Ltd. is focused on advancing semiconductor technologies to address various challenges and improve the performance and reliability of electronic devices. Their recent patents demonstrate their commitment to innovation and their efforts to meet the evolving needs of the industry. |
| | | | |
| − | '''Brief explanation'''
| + | Summary of notable applications: |
| − | The patent application describes a semiconductor cleaning tool that includes a nozzle connected to receive a carrier gas and one or more fluids. The nozzle has separate gas and fluid passageways, with interweaving branches for controlling the flow rate, temperature, on/off state, type of fluid or gas, time period, and supply mode of each branch.
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| | | | |
| − | * The cleaning tool is designed for semiconductor cleaning purposes. | + | * Thermal management systems |
| − | * The tool includes a nozzle with separate gas and fluid passageways. | + | * Heat transfer devices |
| − | * The gas passageway has branches for controlling the flow rate, temperature, on/off state, type of gas, time period, and supply mode. | + | * Cooling systems |
| − | * The fluid passageway also has branches for controlling the flow rate, temperature, on/off state, type of fluid, time period, and supply mode. | + | * Data storage systems |
| − | * The gas and fluid passage branches are arranged in an interweaving pattern within the nozzle. | + | * Non-volatile memory |
| − | * Each gas and fluid passage branch can be controlled independently and separately. | + | * High-density memory |
| − | * The tool allows for precise control of spraying fluids and carrier gas onto the semiconductor surface. | + | * Logic circuits |
| | + | * Neuromorphic computing |
| | + | * Computer memory systems |
| | + | * Solid-state drives (SSDs) |
| | + | * Internet of Things (IoT) devices |
| | + | * Wearable technology |
| | + | * Embedded systems |
| | + | * Automotive electronics |
| | + | * Integrated circuits |
| | + | * Memory devices for electronic devices |
| | + | * Non-volatile memory for data storage |
| | + | * High-density memory for increased storage capacity |
| | + | * Memory storage in electronic devices |
| | + | * Efficient memory storage |
| | + | * Memory devices with improved performance and reliability |
| | + | * Memory devices with increased storage capacity |
| | + | * Compact memory storage |
| | + | * Improved semiconductor assembly connections |
| | + | * Circuit boards with optimized layout for efficient soldering |
| | + | * Efficient and reliable connection between semiconductor assembly and circuit board |
| | + | * Improved performance and reliability of electric devices |
| | + | * Improved memory cell design |
| | + | * Enhanced performance and reliability of memory devices |
| | + | * Increased data storage capacity |
| | + | * Reduced power consumption |
| | + | * Enhanced memory capabilities |
| | + | * Improved stability and reliability in memory operations |
| | + | * Compact and cost-effective memory storage |
| | + | * Improved accuracy and noise cancellation capabilities in analog-to-digital conversion |
| | + | * Enhanced performance and reliability of semiconductor devices |
| | + | * Increased data processing speed |
| | + | * Improved memory storage capabilities |
| | + | * Enhanced functionality of electronic devices |
| | + | * Improved performance and reliability of D flip-flops |
| | + | * Efficient use of transistors with different threshold voltages |
| | + | * Enhanced functionality and flexibility in circuit design |
| | + | * Higher speed and lower power consumption in semiconductor devices |
| | + | * Improved stability and robustness of D flip-flops |
| | + | * Simplified circuit design and layout. |
| | | | |
| − | == Potential Applications ==
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| − | This technology has potential applications in the semiconductor industry for cleaning and maintaining semiconductor surfaces.
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| | | | |
| − | == Problems Solved ==
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| − | The cleaning tool solves the problem of effectively and precisely cleaning semiconductor surfaces by providing separate control over the carrier gas and fluids being sprayed.
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| | | | |
| − | == Benefits ==
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| − | The tool offers the following benefits:
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| − | * Precise control over the flow rate, temperature, on/off state, type of fluid or gas, time period, and supply mode.
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| − | * Efficient and effective cleaning of semiconductor surfaces.
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| − | * Improved maintenance and longevity of semiconductor devices.
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| | | | |
| − | '''Abstract'''
| + | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on December 28th, 2023== |
| − | A semiconductor cleaning tool is provided. The cleaning tool comprises a nozzle. The nozzle is connected with a first inlet to receive a carrier gas and a second inlet to receive one or more fluids. The nozzle comprises a gas passageway connected to the first inlet; and fluid passageway connected to the second inlet. The gas passageway comprises gas passage branches and the fluid passageway comprises fluid passage branches. The gas passage branches and the fluid passage branches are arranged interweavingly in the nozzle. Individual gas/fluid passage branches are controllable indecently and separately including a flow rate, a temperature, an on/off state, a type of fluid(s) or carrier gas, a time period, a supply mode, and/or any other aspects of spraying the fluid(s) and carrier gas through the individual gas passage branches and the individual fluid passage branches.
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| − | ===RAIL SYSTEM FOR WAFER TRANSPORTATION ([[17849038. RAIL SYSTEM FOR WAFER TRANSPORTATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849038]])=== | + | ===WET CLEANING TOOL AND METHOD ([[17847208. WET CLEANING TOOL AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847208]])=== |
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| | '''Main Inventor''' | | '''Main Inventor''' |
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| − | Guancyun Li
| + | Hsu. Tung. Yen |
| | | | |
| | | | |
| − | '''Brief explanation'''
| + | ===RAIL SYSTEM FOR WAFER TRANSPORTATION ([[17849038. RAIL SYSTEM FOR WAFER TRANSPORTATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849038]])=== |
| − | The present disclosure describes a method for installing a rail assembly according to different rail plans. The method involves assembling an overhead raceway module that includes first level raceways extending in one direction and second level raceways extending perpendicular to the first direction. The second level raceways are fastened to the first level raceways. The overhead raceway module is then raised adjacent to a ceiling and installed to the ceiling. Finally, a rail assembly is fastened to the second level raceways, extending lengthwise in the first direction. The width of the overhead raceway module along the second direction is at least three times the width of the rail assembly along the second direction.
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| − | * The method involves assembling an overhead raceway module with first and second level raceways.
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| − | * The second level raceways are fastened to the first level raceways.
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| − | * The overhead raceway module is raised adjacent to a ceiling and installed to the ceiling.
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| − | * A rail assembly is fastened to the second level raceways, extending lengthwise in a specific direction.
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| − | * The width of the overhead raceway module is significantly larger than the width of the rail assembly.
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| | | | |
| − | ==Potential Applications==
| + | '''Main Inventor''' |
| − | * This method can be applied in various industries where rail assemblies are used, such as transportation, logistics, and manufacturing.
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| − | * It can be used to install rail systems for moving heavy objects or equipment.
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| − | * The method can be utilized in the construction industry for installing overhead rail systems for material handling.
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| | | | |
| − | ==Problems Solved==
| + | Guancyun Li |
| − | * The method provides a simplified and efficient way to install rail assemblies according to different rail plans.
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| − | * It allows for flexibility in designing and implementing rail systems in various environments.
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| − | * The method ensures secure and stable installation of the rail assembly to the overhead raceway module.
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| | | | |
| − | ==Benefits==
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| − | * The method saves time and effort in installing rail assemblies, reducing labor costs.
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| − | * It allows for easy customization and modification of rail systems as per specific requirements.
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| − | * The secure installation of the rail assembly ensures safe and reliable transportation of objects or equipment.
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| − |
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| − | '''Abstract'''
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| − | The present disclosure provides a method to install a rail assembly according to different rail plans. A method according to the present disclosure includes assembling an overhead raceway module that includes a plurality of first level raceways extending along a first direction, and a plurality of second level raceways extending along a second direction perpendicular to the first direction, each of the plurality of second level raceways being fastened to the plurality of first level raceways, raising the overhead raceway module adjacent to a ceiling, installing the overhead raceway module to the ceiling, and fastening a rail assembly to the plurality of second level raceways, the rail assembly extending lengthwise along the first direction. A width of the overhead raceway module along the second direction is at least three times a width of the rail assembly along the second direction.
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| | | | |
| | ===Photonic Package and Method of Manufacture ([[17809122. Photonic Package and Method of Manufacture simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809122]])=== | | ===Photonic Package and Method of Manufacture ([[17809122. Photonic Package and Method of Manufacture simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809122]])=== |
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| | Tsung-Fu Tsai | | Tsung-Fu Tsai |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a package that includes a laser diode and various layers and structures to facilitate its operation and connectivity.
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| − |
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| − | * The package includes a bonding layer that directly bonds to the laser diode.
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| − | * A first dielectric layer is placed over the laser diode and is directly bonded to the bonding layer.
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| − | * A first silicon nitride waveguide is embedded in the first dielectric layer and extends over the laser diode.
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| − | * A second dielectric layer is placed over the first silicon nitride waveguide.
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| − | * A silicon waveguide is embedded in the second dielectric layer.
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| − | * An interconnect structure is placed over the silicon waveguide.
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| − | * Conductive features are present to electrically contact the interconnect structure through the first and second dielectric layers.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * Optical communication systems
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| − | * Laser-based medical devices
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| − | * Optical sensing devices
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| − | * Data storage systems
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * Facilitates efficient and reliable electrical connectivity to the laser diode
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| − | * Provides a compact and integrated package for laser diode operation
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| − | * Ensures proper alignment and protection of the waveguides
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * Improved performance and reliability of laser diodes
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| − | * Compact and integrated design for space-saving applications
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| − | * Enhanced electrical connectivity for efficient operation
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| − | * Protection and alignment of waveguides for optimal performance.
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| − |
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| − | '''Abstract'''
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| − | A package includes a laser diode includes a bonding layer; a first dielectric layer over the laser diode, wherein the first dielectric layer is directly bonded to the bonding layer of the laser diode; a first silicon nitride waveguide in the first dielectric layer, wherein the first silicon nitride waveguide extends over the laser diode; a second dielectric layer over the first silicon nitride waveguide; a silicon waveguide in the second dielectric layer; an interconnect structure over the silicon waveguide; and conductive features extending through the first dielectric layer and the second dielectric layer to electrically contact the interconnect structure.
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| | ===LIGHT DEFLECTION STRUCTURE TO INCREASE OPTICAL COUPLING ([[18149325. LIGHT DEFLECTION STRUCTURE TO INCREASE OPTICAL COUPLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18149325]])=== | | ===LIGHT DEFLECTION STRUCTURE TO INCREASE OPTICAL COUPLING ([[18149325. LIGHT DEFLECTION STRUCTURE TO INCREASE OPTICAL COUPLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18149325]])=== |
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| | Chih-Wei Tseng | | Chih-Wei Tseng |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a semiconductor device that includes a dielectric structure, an edge coupler, and a deflector structure. The edge coupler has multiple optical core segments and is located within the dielectric structure. The deflector structure is positioned next to the edge coupler and is designed to redirect an optical signal from one direction to another towards the edge coupler.
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| − |
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| − | * The semiconductor device includes a dielectric structure on a substrate.
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| − | * An edge coupler is present within the dielectric structure and consists of multiple optical core segments.
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| − | * A deflector structure is also within the dielectric structure and is positioned next to the edge coupler.
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| − | * The deflector structure is capable of redirecting an optical signal traveling in one direction towards the edge coupler in a different direction.
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| − |
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| − | == Potential Applications ==
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| − | * Optical communication systems
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| − | * Fiber optic networks
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| − | * Data centers
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| − | * Telecommunications industry
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| − |
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| − | == Problems Solved ==
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| − | * Efficiently redirecting optical signals towards an edge coupler
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| − | * Enhancing the performance of optical communication systems
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| − | * Improving the functionality of fiber optic networks
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| − |
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| − | == Benefits ==
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| − | * Improved signal transmission in optical communication systems
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| − | * Increased efficiency and reliability of fiber optic networks
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| − | * Enhanced performance and functionality of data centers and telecommunications industry
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| − |
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| − | '''Abstract'''
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| − | Various embodiments of the present disclosure are directed towards a semiconductor device including a dielectric structure disposed on a first substrate. An edge coupler is disposed within the dielectric structure and comprises a plurality of optical core segments. A deflector structure is disposed within the dielectric structure and is laterally adjacent to the edge coupler. The deflector structure is configured to redirect an optical signal traveling along a first direction to a second direction towards the edge coupler.
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| | ===METHOD OF MANUFACTURING PHOTO MASKS AND SEMICONDUCTOR DEVICES ([[18103289. METHOD OF MANUFACTURING PHOTO MASKS AND SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18103289]])=== | | ===METHOD OF MANUFACTURING PHOTO MASKS AND SEMICONDUCTOR DEVICES ([[18103289. METHOD OF MANUFACTURING PHOTO MASKS AND SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18103289]])=== |
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| | Wen-Hao CHENG | | Wen-Hao CHENG |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for manufacturing a photo mask used in semiconductor manufacturing. The method involves obtaining an original pattern layout, determining a lower bound for the image-log-slope (ILS), adjusting the sizes of the patterns to decrease the exposure dose while maintaining ILS values above the lower bound, performing an optical proximity correction (OPC) operation on the adjusted patterns to obtain mask data, and manufacturing a photo mask using the mask data.
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| − |
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| − | * The method aims to reduce the exposure dose required for the patterns on the photo mask.
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| − | * The adjustment of pattern sizes ensures that the ILS values remain above a specified lower bound.
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| − | * The OPC operation helps to improve the accuracy of the patterns on the photo mask.
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| − | * The resulting photo mask can be used in the manufacturing of semiconductors.
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| − |
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| − | == Potential Applications ==
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| − | * Semiconductor manufacturing
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| − | * Integrated circuit fabrication
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| − |
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| − | == Problems Solved ==
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| − | * Reducing the exposure dose required for patterns on a photo mask
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| − | * Maintaining acceptable ILS values during pattern size adjustment
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| − | * Improving the accuracy of patterns on a photo mask through OPC
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| − |
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| − | == Benefits ==
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| − | * Lower manufacturing costs due to reduced exposure dose
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| − | * Improved pattern accuracy on the photo mask
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| − | * Enhanced overall quality and performance of semiconductor devices.
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| − |
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| − | '''Abstract'''
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| − | In a method of manufacturing a photo mask, an original pattern layout including a plurality of patterns, each of which is defined by an opaque area, is obtained, a lower bound of an image-log-slope (ILS) is determined, sizes of the plurality of patterns are adjusted such that an exposure dose for the plurality of patterns decreases, while ILS values of the plurality of patterns do not fall below the lower bound of the ILS, an optical proximity correction (OPC) operation is performed on the plurality of patterns of which sizes have been adjusted to obtain mask data, and a photo mask is manufactured by using the mask data.
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| | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING TOOL ([[18107427. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18107427]])=== | | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING TOOL ([[18107427. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18107427]])=== |
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| | Hui-Chun LEE | | Hui-Chun LEE |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method of manufacturing a semiconductor device using a photoresist layer. Here are the key points:
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| − |
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| − | * A photoresist layer is formed on a substrate.
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| − | * The photoresist layer is selectively exposed to actinic radiation.
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| − | * The exposed photoresist layer is heated.
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| − | * During the heating process, a gas is flowed over the photoresist layer.
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| − | * The flow of the gas is varied during the heating process.
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| − | * After heating, the photoresist layer is developed to form a pattern.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * Manufacturing of semiconductor devices.
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| − | * Fabrication of integrated circuits.
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| − | * Production of microchips and electronic components.
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * Provides a method for precise patterning of photoresist layers.
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| − | * Enables the production of complex semiconductor structures.
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| − | * Improves the efficiency and accuracy of semiconductor manufacturing processes.
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * Allows for the creation of intricate patterns on semiconductor devices.
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| − | * Enhances the performance and functionality of electronic components.
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| − | * Increases the yield and quality of semiconductor manufacturing.
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| − | * Reduces production costs and time.
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| − |
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| − | '''Abstract'''
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| − | A method of manufacturing a semiconductor device includes forming a photoresist layer including a photoresist composition over a substrate. The photoresist layer is selectively exposed to actinic radiation. The photoresist layer is heated after selectively exposing the photoresist layer to actinic radiation. A gas is flowed over the photoresist layer during the heating the photoresist layer. A flow of the gas is varied during the heating the photoresist layer, and the photoresist layer is developed after the heating the photoresist layer to form a pattern in the photoresist layer.
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| | ===DATA COMPUTATION CIRCUIT AND METHOD ([[18157252. DATA COMPUTATION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18157252]])=== | | ===DATA COMPUTATION CIRCUIT AND METHOD ([[18157252. DATA COMPUTATION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18157252]])=== |
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| | Chia-Fu LEE | | Chia-Fu LEE |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a circuit that performs multiplication and reformatting operations on input and weight data elements. It includes a multiplier circuit, a summing circuit, a shifting circuit, and an adder tree.
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| − |
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| − | * The multiplier circuit receives signed mantissas of input and weight data elements and generates two's complement products.
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| − | * The summing circuit adds the exponents of each input and weight data element to generate sums.
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| − | * The shifting circuit shifts each product based on the difference between a corresponding sum and a maximum sum.
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| − | * The adder tree generates a mantissa sum from the shifted products.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * Digital signal processing
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| − | * Machine learning algorithms
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| − | * Image and video processing
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| − | * Financial modeling and analysis
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * Efficient multiplication and reformatting of data elements
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| − | * Accurate calculation of sums and mantissa sums
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| − | * Handling of signed mantissas and exponents
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * Improved accuracy and precision in calculations
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| − | * Faster processing speed
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| − | * Reduced circuit complexity
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| − | * Compatibility with various applications and algorithms
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| − |
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| − | '''Abstract'''
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| − | A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.
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| | ===METHOD OF STORING DATA IN MEMORIES ([[17747318. METHOD OF STORING DATA IN MEMORIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17747318]])=== | | ===METHOD OF STORING DATA IN MEMORIES ([[17747318. METHOD OF STORING DATA IN MEMORIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17747318]])=== |
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| | Win-San KHWA | | Win-San KHWA |
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| − |
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| − | '''Brief explanation'''
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| − | The patent application describes a method for storing input data into a memory storage using bit cells. The method involves determining the value of a characterization bit in the input data. Based on the value of the characterization bit, the remaining bits in the input data are written into the bit cells as either a first state or a second state.
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| − |
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| − | * The method determines the value of a characterization bit in the input data.
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| − | * If the characterization bit has a first value, the remaining bits in the input data are written into the bit cells as a first state.
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| − | * If the characterization bit has a second value that is the complement of the first value, the remaining bits in the input data are written into the bit cells as a second state.
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| − | * Reading the bit cell with the first state consumes less energy than reading the bit cell with the second state.
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| − | * Alternatively, the bit cell with the first state has less retention errors than the bit cell with the second state.
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| − |
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| − | Potential applications of this technology:
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| − |
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| − | * Memory storage systems
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| − | * Data storage devices
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| − | * Computer systems
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| − |
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| − | Problems solved by this technology:
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| − |
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| − | * Energy consumption in reading bit cells
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| − | * Retention errors in bit cells
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| − |
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| − | Benefits of this technology:
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| − |
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| − | * Reduced energy consumption
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| − | * Improved reliability and accuracy of data storage
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| − |
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| − | '''Abstract'''
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| − | A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.
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| | ===SENSE AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND SENSING METHOD THEREOF ([[17846035. SENSE AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND SENSING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17846035]])=== | | ===SENSE AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND SENSING METHOD THEREOF ([[17846035. SENSE AMPLIFIER CIRCUIT, MEMORY CIRCUIT, AND SENSING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17846035]])=== |
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| | Jui-Jen Wu | | Jui-Jen Wu |
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| − |
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| − | '''Brief explanation'''
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| − | The abstract describes a sense amplifier circuit that includes a differential amplifier, two switches, and a control line. The differential amplifier amplifies the voltage difference between its output nodes based on the input voltages at its input nodes. The switches are connected to the input and output nodes of the differential amplifier and are controlled by a select signal on the control line. The switches pre-charge the input nodes using the output voltages of the amplifier.
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| − |
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| − | * The sense amplifier circuit includes a differential amplifier, two switches, and a control line.
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| − | * The differential amplifier amplifies the voltage difference between its output nodes based on the input voltages at its input nodes.
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| − | * The switches are connected to the input and output nodes of the differential amplifier.
| |
| − | * The switches pre-charge the input nodes using the output voltages of the amplifier.
| |
| − | * The switches are controlled by a select signal on the control line.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Memory circuits
| |
| − | * Data processing circuits
| |
| − | * Analog-to-digital converters
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Efficient amplification of voltage difference
| |
| − | * Pre-charging of input nodes
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Improved performance and accuracy in memory and data processing circuits
| |
| − | * Higher speed and efficiency in analog-to-digital converters
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.
| |
| | | | |
| | ===GAS DISTRIBUTION RING FOR PROCESS CHAMBER ([[17851385. GAS DISTRIBUTION RING FOR PROCESS CHAMBER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851385]])=== | | ===GAS DISTRIBUTION RING FOR PROCESS CHAMBER ([[17851385. GAS DISTRIBUTION RING FOR PROCESS CHAMBER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851385]])=== |
| Line 335: |
Line 143: |
| | Po-Hsiang Wang | | Po-Hsiang Wang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present disclosure describes an integrated chip processing tool that includes a gas distribution ring. This gas distribution ring is designed to extend along the perimeter of a process chamber and is made up of a lower ring and an upper ring.
| |
| − |
| |
| − | * The lower ring of the gas distribution ring has gas inlets arranged along its bottom surface and gas conveyance channels arranged along its upper surface. These gas conveyance channels are positioned directly over the gas inlets.
| |
| − | * The upper ring is placed on top of the lower ring and covers the gas conveyance channels.
| |
| − | * Gas outlets are arranged along the opposing ends of the gas conveyance channels.
| |
| − | * The gas conveyance paths, which extend between the gas inlets and the gas outlets, have approximately equal lengths.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * This integrated chip processing tool can be used in the manufacturing of integrated circuits and other electronic devices.
| |
| − | * It can be utilized in various semiconductor fabrication processes, such as deposition, etching, and cleaning.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * The gas distribution ring ensures a more uniform distribution of gas within the process chamber, leading to improved process control and uniformity.
| |
| − | * The equal lengths of the gas conveyance paths help to prevent any variations or inconsistencies in the gas flow, resulting in more reliable and predictable processing.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * The integrated chip processing tool provides better control over the gas distribution, leading to improved process performance and yield.
| |
| − | * The equal lengths of the gas conveyance paths help to minimize any potential variations in the gas flow, ensuring consistent and reliable processing.
| |
| − | * The gas distribution ring design simplifies the gas distribution system, making it easier to manufacture and maintain.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure relates to an integrated chip processing tool. The integrated chip processing tool includes a gas distribution ring configured to extend along a perimeter of a process chamber. The gas distribution ring includes a lower ring extending around the process chamber. The lower ring has a plurality of gas inlets arranged along a bottom surface of the lower ring and a plurality of gas conveyance channels arranged along an upper surface of the lower ring directly over the plurality of gas inlets. The gas distribution ring further includes an upper ring disposed on the upper surface of the lower ring and covering the plurality of gas conveyance channels. A plurality of gas outlets are arranged along opposing ends of the plurality of gas conveyance channels. A plurality of gas conveyance paths extending between the plurality of gas inlets and the plurality of gas outlets have approximately equal lengths.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[17849720. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849720]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[17849720. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849720]])=== |
| Line 370: |
Line 151: |
| | Bo-Jiun Lin | | Bo-Jiun Lin |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for manufacturing a semiconductor device using a transition metal layer and a chalcogen-containing fluid. The method involves the following steps:
| |
| − |
| |
| − | * A transition metal layer is formed over a substrate in a reaction chamber.
| |
| − | * A chalcogen-containing fluid is flowed into the reaction chamber.
| |
| − | * A heating process is performed in the reaction chamber, causing the transition metal layer to transform into a two-dimensional (2D) material layer over the substrate.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Manufacturing of semiconductor devices.
| |
| − | * Creation of two-dimensional (2D) material layers for various electronic applications.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for manufacturing semiconductor devices using a transition metal layer and a chalcogen-containing fluid.
| |
| − | * Enables the transformation of the transition metal layer into a two-dimensional (2D) material layer.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Simplifies the manufacturing process of semiconductor devices.
| |
| − | * Allows for the creation of two-dimensional (2D) material layers with improved properties.
| |
| − | * Offers potential advancements in electronic applications utilizing two-dimensional (2D) materials.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for manufacturing a semiconductor device includes the following steps. A transition metal layer is formed over a substrate in a reaction chamber; a chalcogen-containing fluid is flowed into the reaction chamber; and a heating process is performed in the reaction chamber over the transition metal layer with the chalcogen-containing fluid to transform the transition metal layer into a two-dimensional (2D) material layer over the substrate.
| |
| | | | |
| | ===ANISOTROPIC WET ETCHING IN PATTERNING ([[17808175. ANISOTROPIC WET ETCHING IN PATTERNING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17808175]])=== | | ===ANISOTROPIC WET ETCHING IN PATTERNING ([[17808175. ANISOTROPIC WET ETCHING IN PATTERNING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17808175]])=== |
| Line 404: |
Line 159: |
| | Tefu Yeh | | Tefu Yeh |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for removing a metal layer from one structure while preserving the metal layer on another structure. The method involves using a chemical etchant that does not penetrate a photolithographic layer.
| |
| − |
| |
| − | * The method involves providing two structures with metal layers.
| |
| − | * A patterned photolithographic layer is formed over the metal layer on the first structure.
| |
| − | * The metal layer on the second structure is removed using a wet etch process.
| |
| − | * The wet etch process uses a chemical etchant that does not penetrate the photolithographic layer.
| |
| − | * After the wet etch process, the remaining metal ratio is calculated as the distance X over the distance Y.
| |
| − | * The remaining metal ratio must be less than 179 and greater than 1.
| |
| − | * X is the distance from the edge of the metal layer on the first structure to the edge of the channel region in the second structure.
| |
| − | * Y is the distance from the edge of the metal layer on the first structure to the edge of the metal layer formed over the channel region in the first structure.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Semiconductor manufacturing
| |
| − | * Microelectronics fabrication
| |
| − | * Integrated circuit production
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Precise removal of metal layers from specific structures without damaging other structures
| |
| − | * Preservation of metal layers on desired structures during wet etch processes
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Improved control and accuracy in metal layer removal
| |
| − | * Reduction in manufacturing defects and yield losses
| |
| − | * Cost savings in semiconductor and microelectronics production
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed is a method comprising: providing at least two structures with a metal layer over each; forming a patterned photolithographic layer over the metal layer over the first structure; removing the metal layer from the second structure via wet etch operations using a chemical etchant that is resistant to penetration into the photolithographic layer; and achieving, after wet etch operations, a remaining metal ratio of a distance X over a distance Y that is less than 179 and greater than 1, wherein X is the distance from a first line extending from an edge of the metal layer over the first structure to a second line extending from an edge of a channel region in the second structure, and Y is a second distance from the first line to a third line extending from an edge of the metal layer formed over the channel region in the first structure.
| |
| | | | |
| | ===METHOD FOR FORMING A CONTACT PLUG WITH IMPROVED CONTACT METAL SEALING ([[17847863. METHOD FOR FORMING A CONTACT PLUG WITH IMPROVED CONTACT METAL SEALING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847863]])=== | | ===METHOD FOR FORMING A CONTACT PLUG WITH IMPROVED CONTACT METAL SEALING ([[17847863. METHOD FOR FORMING A CONTACT PLUG WITH IMPROVED CONTACT METAL SEALING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847863]])=== |
| Line 444: |
Line 167: |
| | Chung-Liang CHENG | | Chung-Liang CHENG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for forming a metal contact plug on a substrate. The method involves several steps, including etching the substrate to create a contact hole, forming a dielectric liner layer on the sidewall of the contact hole, and then forming the metal contact plug within the hole. Additionally, an implantation process is performed on the substrate to introduce dopants with a larger atomic size than silicon.
| |
| − |
| |
| − | * The method involves etching a substrate to create a contact hole.
| |
| − | * A dielectric liner layer is formed on the sidewall of the contact hole.
| |
| − | * A metal contact plug is formed within the contact hole.
| |
| − | * An implantation process is performed to introduce dopants with a larger atomic size than silicon into the substrate.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Semiconductor manufacturing
| |
| − | * Integrated circuit fabrication
| |
| − | * Microelectronics industry
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for forming metal contact plugs on substrates
| |
| − | * Improves the reliability and performance of integrated circuits
| |
| − | * Enables the integration of different materials with silicon substrates
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Simplifies the process of forming metal contact plugs
| |
| − | * Enhances the electrical properties of the contact plugs
| |
| − | * Enables the use of different materials in semiconductor devices
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method is provided for forming a metal contact plug. In one step, a substrate, which is an Si substrate or an SiOsubstrate, is etched to form a contact hole. In one step, a dielectric liner layer is formed on a sidewall of the contact hole. In one step, the metal contact plug that is in contact with the dielectric liner layer is formed in the contact hole. In one step, an implantation process is performed on the substrate, so as to implant dopants having an atomic size greater than that of Si into the substrate.
| |
| | | | |
| | ===Semiconductor Packages and Methods of Forming the Same ([[17808705. Semiconductor Packages and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17808705]])=== | | ===Semiconductor Packages and Methods of Forming the Same ([[17808705. Semiconductor Packages and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17808705]])=== |
| Line 481: |
Line 175: |
| | Sey-Ping Sun | | Sey-Ping Sun |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method for bonding semiconductor dies to a substrate and filling the gap between them with a thermally conductive material. A dielectric layer is then deposited over the dies and the conductive region.
| |
| − |
| |
| − | * The method involves bonding semiconductor dies to a substrate.
| |
| − | * A gap is left between the dies.
| |
| − | * The gap is filled with a metal material to create a thermally conductive region.
| |
| − | * A dielectric layer is deposited over the dies and the conductive region.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in the manufacturing of electronic devices such as integrated circuits and microprocessors.
| |
| − | * It can improve the thermal management of these devices, allowing for better heat dissipation and potentially increasing their performance and reliability.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The method solves the problem of heat buildup in semiconductor devices by providing a thermally conductive region between the dies.
| |
| − | * It addresses the challenge of bonding multiple dies to a substrate while maintaining thermal efficiency.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The use of a thermally conductive region improves the heat dissipation capabilities of the semiconductor device.
| |
| − | * The method allows for efficient bonding of multiple dies to a substrate, enabling the integration of complex electronic systems.
| |
| − | * It can enhance the overall performance and reliability of electronic devices by reducing the risk of overheating.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes bonding a first semiconductor die to a semiconductor substrate; bonding a second semiconductor die to the semiconductor substrate, wherein the second semiconductor die is laterally separated from the first semiconductor die by a gap; filling the gap between the first semiconductor die and the second semiconductor die with a metal material to form a thermally conductive region; and depositing a first dielectric layer over the first semiconductor die, the second semiconductor die, and the thermally conductive region.
| |
| | | | |
| | ===SEMICONDUCTOR PACKAGE AND METHOD ([[17809039. SEMICONDUCTOR PACKAGE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809039]])=== | | ===SEMICONDUCTOR PACKAGE AND METHOD ([[17809039. SEMICONDUCTOR PACKAGE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809039]])=== |
| Line 513: |
Line 183: |
| | Ban-Li Wu | | Ban-Li Wu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor package that includes heat dissipation systems and a method of forming it. The package consists of integrated circuit dies, an encapsulant, and a redistribution structure. The redistribution structure has heat dissipation systems that are electrically isolated from the rest of the structure. Each heat dissipation system includes metal pads and metal vias connecting them.
| |
| − |
| |
| − | * The semiconductor package includes one or more heat dissipation systems.
| |
| − | * The package contains integrated circuit dies, an encapsulant, and a redistribution structure.
| |
| − | * The redistribution structure has heat dissipation systems that are electrically isolated.
| |
| − | * Each heat dissipation system consists of metal pads and metal vias connecting them.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in various electronic devices that require efficient heat dissipation, such as smartphones, laptops, and servers.
| |
| − | * It can be applied in high-performance computing systems, where heat management is crucial for optimal performance.
| |
| − | * The semiconductor package can be used in automotive electronics to ensure reliable operation under high-temperature conditions.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The heat dissipation systems in the semiconductor package address the issue of excessive heat generation in integrated circuits, which can lead to performance degradation and even failure.
| |
| − | * By providing electrically isolated heat dissipation systems, the package prevents interference with other components and ensures reliable operation.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The heat dissipation systems in the semiconductor package improve the overall thermal management of the integrated circuits, enhancing their performance and longevity.
| |
| − | * The electrically isolated heat dissipation systems prevent electrical interference and improve the reliability of the package.
| |
| − | * The method of forming the semiconductor package allows for efficient and cost-effective manufacturing processes.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor package including one or more heat dissipation systems and a method of forming are provided. The semiconductor package may include one or more integrated circuit dies, an encapsulant surrounding the one or more integrated circuit dies, a redistribution structure over the one or more integrated circuit dies and the encapsulant. The redistribution structure may include one or more heat dissipation systems, which are electrically isolated from remaining portions of the redistribution structure. Each heat dissipation system may include a first metal pad, a second metal pad, and one or more metal vias connecting the first metal pad to the second metal pad.
| |
| | | | |
| | ===Cooling Cover and Packaged Semiconductor Device Including the Same ([[17809128. Cooling Cover and Packaged Semiconductor Device Including the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809128]])=== | | ===Cooling Cover and Packaged Semiconductor Device Including the Same ([[17809128. Cooling Cover and Packaged Semiconductor Device Including the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809128]])=== |
| Line 546: |
Line 191: |
| | Chung-Jung Wu | | Chung-Jung Wu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a patent application for cooling covers with trapezoidal cooling chambers for semiconductor devices. The cooling cover includes an inlet, an outlet, and a cooling chamber that has a trapezoidal shape in a cross-sectional view.
| |
| − |
| |
| − | * The patent application is for cooling covers designed specifically for packaged semiconductor devices.
| |
| − | * The cooling cover includes an inlet and an outlet to allow for the flow of cooling fluid.
| |
| − | * The cooling chamber within the cover is in fluid communication with the inlet and the outlet.
| |
| − | * The cooling chamber is designed with a trapezoidal shape in a cross-sectional view.
| |
| − | * The trapezoidal shape of the cooling chamber is likely to optimize the cooling efficiency for the semiconductor device.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Cooling covers with trapezoidal cooling chambers can be used in various semiconductor devices, such as microprocessors, memory chips, and power electronics.
| |
| − | * This technology can be applied in industries that heavily rely on semiconductor devices, including consumer electronics, automotive, aerospace, and telecommunications.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Overheating is a common issue in semiconductor devices, which can lead to reduced performance and even failure.
| |
| − | * Traditional cooling methods may not be efficient enough to adequately cool semiconductor devices.
| |
| − | * The trapezoidal cooling chambers in the cooling covers aim to solve the problem of inefficient cooling by optimizing the flow of cooling fluid.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The trapezoidal shape of the cooling chamber is expected to enhance the cooling efficiency of the semiconductor device.
| |
| − | * Improved cooling can help prevent overheating, prolong the lifespan of the semiconductor device, and maintain optimal performance.
| |
| − | * The cooling covers can be easily integrated into existing semiconductor device designs, providing a cost-effective cooling solution.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Cooling covers including trapezoidal cooling chambers for cooling packaged semiconductor devices and methods of forming the same are disclosed. In an embodiment, a cooling cover for a semiconductor device includes an inlet; an outlet; and a cooling chamber in fluid communication with the inlet and the outlet, the cooling chamber having a trapezoidal shape in a cross-sectional view.
| |
| | | | |
| | ===INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD ([[17929397. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17929397]])=== | | ===INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD ([[17929397. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17929397]])=== |
| Line 580: |
Line 199: |
| | Chin-Shen LIN | | Chin-Shen LIN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes an integrated circuit (IC) device that includes a power control circuit and front and back side metal layers. It also includes first and second feed through vias (FTVs) that connect the front and back side power rails. The power control circuit can control the connection between the front side power rails.
| |
| − |
| |
| − | * The IC device includes a power control circuit, front and back side metal layers, and feed through vias (FTVs).
| |
| − | * The FTVs connect the front and back side power rails.
| |
| − | * The power control circuit can control the connection between the front side power rails.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Integrated circuit devices
| |
| − | * Power control circuits
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Efficient power control in integrated circuit devices
| |
| − | * Improved connectivity between front and back side power rails
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Enhanced functionality of integrated circuit devices
| |
| − | * Improved power management capabilities
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An integrated circuit (IC) device includes a substrate with a power control circuit, front and back side metal layers, and first and second feed through vias (FTVs). The front side metal layer has first and second front side power rails. The back side metal layer has first and second back side power rails. The first FTV extends through the substrate, and couples the first front side power rail to the first back side power rail. The second FTV extends through the substrate, and couples the second front side power rail to the second back side power rail. The power control circuit is coupled to the first and second front side power rails, and is controllable to electrically connect the first front side power rail to the second front side power rail, or electrically disconnect the first front side power rail from the second front side power rail.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING ([[17809432. SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809432]])=== | | ===SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING ([[17809432. SEMICONDUCTOR DEVICE AND METHODS OF MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809432]])=== |
| Line 610: |
Line 207: |
| | Yu-Lun LU | | Yu-Lun LU |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a patent application that presents techniques and apparatuses for a stacked-die structure with different operating voltages for two integrated circuit devices. The first integrated circuit device includes a seal ring structure that eliminates the use of diodes and electrically isolates well structures, reducing leakage paths. The seal ring structure includes an interconnect structure that connects different layers of the first integrated circuit device, preventing moisture and cracking from penetrating the stacked-die structure.
| |
| − |
| |
| − | * The patent application describes a stacked-die structure with different operating voltages for two integrated circuit devices.
| |
| − | * The first integrated circuit device includes a seal ring structure that eliminates the need for diodes.
| |
| − | * The seal ring structure also electrically isolates well structures, reducing leakage paths.
| |
| − | * An interconnect structure connects different layers of the first integrated circuit device, forming part of the seal ring structure.
| |
| − | * The interconnect structure helps prevent moisture and cracking from penetrating the stacked-die structure.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be applied in the manufacturing of stacked-die structures in various electronic devices, such as smartphones, tablets, and computers.
| |
| − | * It can be used in integrated circuits that require different operating voltages for different components.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The patent application addresses the issue of leakage paths in stacked-die structures by eliminating the use of diodes and electrically isolating well structures.
| |
| − | * It also solves the problem of moisture and cracking penetrating the stacked-die structure by utilizing the interconnect structure as part of the seal ring structure.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The elimination of diodes and the electrical isolation of well structures reduce leakage paths, improving the overall performance and reliability of the stacked-die structure.
| |
| − | * The interconnect structure used in the seal ring structure helps prevent moisture and cracking, enhancing the durability and longevity of the stacked-die structure.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Some implementations described herein provide techniques and apparatuses for a stacked-die structure including a first integrated circuit device over a second integrated circuit device, where an operating voltage of the first integrated circuit device is different relative to an operating voltage of the second integrated circuit device. The first integrated circuit device includes a first portion of a seal ring structure of the stacked-die structure. The first portion includes an interconnect structure that connects a backside redistribution layer of the first integrated circuit device with first metal layers of the first integrated circuit device. The seal ring structure including the interconnect structure eliminates the use of diodes and electrically isolates well structures of the first integrated circuit device to reduce leakage paths relative to a stacked-die structure having a seal ring structure including a diode within the stacked-die structure. Furthermore, use of the interconnect structure as part of the seal ring structure substantially eliminates moisture and/or cracking from penetrating the stacked-die structure.
| |
| | | | |
| | ===SEMICONDUCTOR PACKAGING ([[17849300. SEMICONDUCTOR PACKAGING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849300]])=== | | ===SEMICONDUCTOR PACKAGING ([[17849300. SEMICONDUCTOR PACKAGING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849300]])=== |
| Line 642: |
Line 215: |
| | Tien-Chung YANG | | Tien-Chung YANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present disclosure describes a structure and method for joining semiconductor packages. The structure includes an adhesion layer, a first joint pad, a film layer with a slanted sidewall, a solder ball, and a second joint pad of a second semiconductor package.
| |
| − |
| |
| − | * The structure includes an adhesion layer in contact with a first semiconductor package.
| |
| − | * A first joint pad is in contact with the adhesion layer.
| |
| − | * A film layer is disposed on the first semiconductor package and the first joint pad.
| |
| − | * The film layer has a slanted sidewall that covers an end portion of the adhesion layer and a first portion of the first joint pad.
| |
| − | * The slanted sidewall exposes a second portion of the first joint pad.
| |
| − | * A solder ball is attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Semiconductor packaging and assembly
| |
| − | * Electronics manufacturing
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a structure and method for joining semiconductor packages
| |
| − | * Ensures proper adhesion between packages
| |
| − | * Facilitates electrical connections between packages
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Improved reliability and performance of semiconductor packages
| |
| − | * Simplified manufacturing process
| |
| − | * Enhanced electrical connectivity between packages
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure describes a structure that joins semiconductor packages and a method for forming the structure. The structure includes an adhesion layer in contact with a first semiconductor package and a first joint pad in contact with the adhesion layer. The structure further includes a film layer disposed on the first semiconductor package and the first joint pad, where the film layer includes a slanted sidewall, the slanted sidewall covers an end portion of the adhesion layer and a first portion of the first joint pad, and the slanted sidewall exposes a second portion of the first joint pad. The structure further includes a solder ball attached to the second portion of the first joint pad and a second joint pad of a second semiconductor package.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD ([[17848605. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848605]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD ([[17848605. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848605]])=== |
| Line 680: |
Line 223: |
| | Kai-Qiang Wen | | Kai-Qiang Wen |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a patent application for a FinFET transistor with an embedded resistor. The resistor is located in the fin between the source epitaxial region and the source contact. A control contact can be used to change the resistivity of the resistor. The edge gates of the FinFET transistor are replaced with insulating structures. Multiple FinFET/embedded resistor combinations can be used together in a common drain/common source contact design.
| |
| − |
| |
| − | * FinFET transistor with embedded resistor in the fin between source epitaxial region and source contact
| |
| − | * Control contact used to change the resistivity of the embedded resistor
| |
| − | * Edge gates of the FinFET transistor replaced with insulating structures
| |
| − | * Multiple FinFET/embedded resistor combinations can be used in a common drain/common source contact design
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Integrated circuits
| |
| − | * Semiconductor devices
| |
| − | * Transistor technology
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Improved performance and functionality of FinFET transistors
| |
| − | * Enhanced control over resistivity in the transistor design
| |
| − | * Simplified transistor structure with insulating structures replacing edge gates
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Increased efficiency and reliability of integrated circuits
| |
| − | * Improved control over resistivity for better circuit design
| |
| − | * Simplified transistor structure for easier manufacturing and integration
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Embodiments include a FinFET transistor including an embedded resistor disposed in the fin between the source epitaxial region and the source contact. A control contact may be used to bias the embedded resistor, thereby changing the resistivity of the resistor. Edge gates of the FinFET transistor may be replaced with insulating structures. Multiple ones of the FinFET/embedded resistor combination may be utilized together in a common drain/common source contact design.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17849725. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849725]])=== | | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17849725. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849725]])=== |
| Line 714: |
Line 231: |
| | Li-Zhen Yu | | Li-Zhen Yu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device that consists of multiple stacks of nanostructures, a gate structure, source and drain structures, and fin structures.
| |
| − | * The device includes multiple stacks of nanostructures that are stacked on top of each other.
| |
| − | * A gate structure wraps around the nanostructures and extends between the stacks.
| |
| − | * Source and drain structures are present in the device.
| |
| − | * The device also includes fin structures that are placed on top of the stacks.
| |
| − | * The first surface of the gate structure between the stacks is aligned with the first surfaces of the fin structures facing the nanostructures or between the first surfaces of the fin structures and the nanostructures.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − | * This semiconductor device can be used in various electronic devices such as smartphones, tablets, and computers.
| |
| − | * It can be utilized in the manufacturing of high-performance processors and memory chips.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − | * The device addresses the need for improved performance and efficiency in semiconductor devices.
| |
| − | * It solves the challenge of integrating multiple nanostructures and fin structures in a compact and efficient manner.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − | * The device offers enhanced performance and efficiency compared to traditional semiconductor devices.
| |
| − | * It allows for the integration of multiple nanostructures and fin structures, enabling higher density and functionality.
| |
| − | * The coplanar alignment of the gate structure and fin structures improves the overall performance and reliability of the device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME ([[17847450. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847450]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME ([[17847450. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847450]])=== |
| Line 746: |
Line 239: |
| | Chih-Kuan Yu | | Chih-Kuan Yu |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The present disclosure describes a semiconductor device with a multi-gate structure. The device includes a substrate, a doped region, a gate electrode, a source region, a drain region, and a shallow trench isolation (STI) structure.
| |
| − |
| |
| − | * The device has a substrate and a doped region within the substrate.
| |
| − | * A gate electrode is placed over the doped region.
| |
| − | * The doped region also contains a source region and a drain region.
| |
| − | * The source and drain regions are surrounded by a shallow trench isolation (STI) structure.
| |
| − | * A first doped liner separates the STI structure from the source and drain regions.
| |
| − | * A second doped liner is placed along the STI structure, separated from the first doped liner by the STI structure.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * This multi-gate structure can be used in various semiconductor devices, such as transistors, to improve their performance and efficiency.
| |
| − | * It can be applied in integrated circuits, microprocessors, and other electronic devices that require high-speed and low-power operation.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * The multi-gate structure helps to reduce leakage current and improve control over the flow of electrons in the semiconductor device.
| |
| − | * It minimizes the impact of parasitic capacitance and resistance, leading to enhanced performance and reduced power consumption.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * The multi-gate structure provides better control over the flow of electrons, resulting in improved device performance and efficiency.
| |
| − | * It helps to reduce power consumption and increase battery life in electronic devices.
| |
| − | * The technology enables the development of smaller and more compact semiconductor devices without compromising their functionality.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | The present disclosure relates to semiconductor device with a multi-gate structure. The semiconductor device includes a substrate and a doped region disposed within the substrate. A gate electrode is disposed over the doped region, and a source region and a drain region are disposed within the doped region. A shallow trench isolation (STI) structure is disposed within the substrate and laterally surrounds the source region and the drain region. A first doped liner is disposed along the STI structure, where the first doped liner separates the STI structure from the source region and the drain region. A second doped liner is disposed along the STI structure, where the second doped liner is separated from the first doped liner by the STI structure above a bottom surface of the STI structure.
| |
| | | | |
| | ===DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF ([[17850477. DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850477]])=== | | ===DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF ([[17850477. DEEP TRENCH ISOLATION STRUCTURE AND METHODS FOR FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850477]])=== |
| Line 783: |
Line 247: |
| | Kai-Yun YANG | | Kai-Yun YANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a patent application for a Deep Trench Isolation (DTI) structure in a semiconductor substrate. The DTI structure includes an isolation layer made of a p-type semiconductor material, with sidewall portions in contact with the substrate and a bottom portion in contact with a connection feature. The connection feature is connected to an interconnect structure and can apply a bias to the isolation layer to achieve controllable passivation in the substrate.
| |
| − |
| |
| − | * The patent application describes a DTI structure formed in a semiconductor substrate.
| |
| − | * The DTI structure includes an isolation layer made of a p-type semiconductor material.
| |
| − | * Sidewall portions of the isolation layer are in contact with the semiconductor substrate.
| |
| − | * A bottom portion of the isolation layer is in contact with a connection feature.
| |
| − | * The connection feature is connected to an interconnect structure.
| |
| − | * The connection feature can apply a bias to the isolation layer to achieve controllable passivation in the semiconductor substrate.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Semiconductor manufacturing
| |
| − | * Integrated circuits
| |
| − | * Electronic devices
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Provides a method for achieving controllable passivation in a semiconductor substrate.
| |
| − | * Improves isolation between components in a semiconductor device.
| |
| − | * Enhances the performance and reliability of integrated circuits.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Enables better control over the passivation process in semiconductor substrates.
| |
| − | * Improves the isolation capabilities of the DTI structure.
| |
| − | * Enhances the overall performance and reliability of semiconductor devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A Deep Trench Isolation (DTI) structure is disclosed. A DTI structure formed in a semiconductor substrate. The DIT structure includes an isolation layer and filling material. The isolation layer is formed from a p-type semiconductor material. Sidewall portions of the isolation layer are in contact with the semiconductor substrate. A bottom portion of the isolation layer is in contact with a connection feature, which is connected to an interconnect structure and configured to apply a bias to the isolation layer of the DTI structure to achieve a controllable passivation in the semiconductor substrate.
| |
| | | | |
| | ===MIM CAPACITOR AND METHOD OF FORMING THE SAME ([[17849930. MIM CAPACITOR AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849930]])=== | | ===MIM CAPACITOR AND METHOD OF FORMING THE SAME ([[17849930. MIM CAPACITOR AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849930]])=== |
| Line 819: |
Line 255: |
| | Hsing-Lien LIN | | Hsing-Lien LIN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a metal-insulator-metal (MIM) capacitor and the methods used to create it. Here are the key points:
| |
| − |
| |
| − | * The method involves creating an opening in one or more dielectric layers.
| |
| − | * A layer is deposited in the opening and on the dielectric layers.
| |
| − | * An anisotropic etch process is used to remove parts of the layer on horizontal surfaces.
| |
| − | * The opening is extended to a deeper depth in the dielectric layers.
| |
| − | * The layer is removed.
| |
| − | * The opening is further extended to an even deeper depth in the dielectric layers.
| |
| − | * Finally, a MIM capacitor is formed in the opening.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Integrated circuits and semiconductor devices
| |
| − | * Energy storage systems
| |
| − | * Capacitive sensors
| |
| − | * Radio frequency (RF) devices
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for creating a metal-insulator-metal (MIM) capacitor with precise dimensions and control over the depth of the opening.
| |
| − | * Enables the formation of a MIM capacitor with improved performance and reliability.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Allows for the creation of MIM capacitors with high capacitance density.
| |
| − | * Provides better control over the dimensions and depth of the capacitor, leading to improved performance.
| |
| − | * Enhances the reliability and stability of the MIM capacitor.
| |
| − | * Enables the integration of MIM capacitors into various electronic devices and systems.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A metal-insulator-metal (MIM) capacitor and methods of forming the same are described. In some embodiments, the method includes forming an opening having a first depth in one or more dielectric layers, depositing a layer in the opening and on the one or more dielectric layers, performing an anisotropic etch process to remove portions of the layer formed on horizontal surfaces, extending the opening to a second depth in the one or more dielectric layers, removing the layer, extending the opening to a third depth in the one or more dielectric layers, and forming a MIM capacitor in the opening.
| |
| | | | |
| | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[17809099. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809099]])=== | | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[17809099. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809099]])=== |
| Line 860: |
Line 263: |
| | Wan-Jyun SYUE | | Wan-Jyun SYUE |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a high-voltage transistor design that uses planar active regions instead of fin active regions to reduce the surface area in contact with surrounding dielectric layers. This reduces charge trapping and improves performance stability and operational lifetime of the transistor.
| |
| − |
| |
| − | * The high-voltage transistor includes planar active regions for source/drain and channel regions.
| |
| − | * Planar active regions replace fin active regions to minimize contact with surrounding dielectric layers.
| |
| − | * This reduces the interface surface area between silicon-based active regions and oxide-based dielectric layers.
| |
| − | * The reduced interface surface area decreases charge trapping in the transistor.
| |
| − | * The design improves performance stability and extends the operational lifetime of the high-voltage transistor.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * High-voltage transistors used in power electronics.
| |
| − | * Transistors used in electric vehicles and renewable energy systems.
| |
| − | * Integrated circuits for industrial automation and control systems.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Charge trapping in high-voltage transistors.
| |
| − | * Performance instability and reduced operational lifetime.
| |
| − | * Surface area contact with surrounding dielectric layers.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Improved performance stability of high-voltage transistors.
| |
| − | * Extended operational lifetime of high-voltage transistors.
| |
| − | * Enhanced reliability and efficiency of power electronics systems.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.
| |
| | | | |
| | ===MULTILAYER GATE ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME ([[17846948. MULTILAYER GATE ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17846948]])=== | | ===MULTILAYER GATE ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME ([[17846948. MULTILAYER GATE ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17846948]])=== |
| Line 895: |
Line 271: |
| | Hong-Chih CHEN | | Hong-Chih CHEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device structure with multiple gate structures and a multilayer gate isolation structure. The multilayer gate isolation structure includes two insulating features, one adjacent to the gate structures and another separating the substrate from the first insulating feature. The second insulating feature has a different material and lower dielectric constant or etch resistance than the first insulating feature.
| |
| − |
| |
| − | * The semiconductor device structure includes first and second gate structures formed over a semiconductor substrate.
| |
| − | * A multilayer gate isolation structure separates the first and second gate structures.
| |
| − | * The multilayer gate isolation structure includes a first insulating feature adjacent to the upper portions of the gate structures.
| |
| − | * A second insulating feature separates the semiconductor substrate from the first insulating feature.
| |
| − | * The material of the second insulating feature is different from the first insulating feature.
| |
| − | * The second insulating feature has a lower dielectric constant or lower etch resistance than the first insulating feature.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Semiconductor manufacturing industry
| |
| − | * Electronics industry
| |
| − | * Integrated circuit design and fabrication
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Improved isolation between gate structures
| |
| − | * Enhanced performance and reliability of semiconductor devices
| |
| − | * Reduction in cross-talk and interference between gate structures
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Higher efficiency and functionality of semiconductor devices
| |
| − | * Improved signal integrity and performance
| |
| − | * Enhanced manufacturing process and yield
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes first and second gate structures formed over a semiconductor substrate and a multilayer gate isolation structure separating the first gate structure from the second gate structure. The multilayer gate isolation structure includes a first insulating feature adjacent to upper portions of the first gate structure and the second gate structure, and a second insulating feature separating the semiconductor substrate from the first insulating feature. The material of the second insulating feature is different than that of the first insulating feature. The second insulating feature has a lower dielectric constant or lower etch resistance than the first insulating feature.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17847075. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847075]])=== | | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17847075. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847075]])=== |
| Line 931: |
Line 279: |
| | Wei Ju LEE | | Wei Ju LEE |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract of the patent application describes a method for forming a channel region above a substrate and growing source/drain regions on either side of the channel region. A gate structure and source/drain contacts are also formed.
| |
| − |
| |
| − | * The method involves forming a channel region above a substrate.
| |
| − | * The channel region has a length extending in a specific direction.
| |
| − | * Epitaxial growing is used to create a plurality of source/drain regions on either side of the channel region.
| |
| − | * A gate structure is formed to surround the channel region.
| |
| − | * A plurality of source/drain contacts are formed on the source/drain regions.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | This technology could have potential applications in various fields, including:
| |
| − |
| |
| − | * Semiconductor industry
| |
| − | * Electronics manufacturing
| |
| − | * Integrated circuit design
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | The technology addresses several problems in the field, such as:
| |
| − |
| |
| − | * Improving the performance and efficiency of semiconductor devices
| |
| − | * Enhancing the functionality of integrated circuits
| |
| − | * Enabling the production of smaller and more powerful electronic devices
| |
| − |
| |
| − | == Benefits ==
| |
| − | The technology offers several benefits, including:
| |
| − |
| |
| − | * Enhanced performance and efficiency of semiconductor devices
| |
| − | * Improved functionality and capabilities of integrated circuits
| |
| − | * Ability to create smaller and more powerful electronic devices
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes forming a channel region above a ()-orientated substrate and having a length extending in a <> direction; epitaxial growing a plurality of source/drain regions on either side the channel region; forming a gate structure surrounding the channel region; forming a plurality of source/drain contacts on the source/drain regions.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME ([[17848406. SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848406]])=== | | ===SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME ([[17848406. SEMICONDUCTOR DEVICES AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848406]])=== |
| Line 972: |
Line 287: |
| | Pei Yun Chung | | Pei Yun Chung |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for forming a semiconductor device using wet etching processes and cleaning steps. Here is a simplified explanation of the abstract:
| |
| − |
| |
| − | * A metal layer with a silicon-containing pattern is provided.
| |
| − | * A first wet etching process is performed using a solution containing a base and an oxidant to clean the metal layer's surface.
| |
| − | * Multiple cycles are performed, each consisting of a second wet etching process and a cleaning process.
| |
| − | * The second wet etching process uses a solution containing an acid and an oxidant to remove the metal layer.
| |
| − | * A cleaning process is performed.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | This technology can be applied in various semiconductor device manufacturing processes, including but not limited to:
| |
| − |
| |
| − | * Integrated circuits (ICs)
| |
| − | * Transistors
| |
| − | * Diodes
| |
| − | * Solar cells
| |
| − | * Sensors
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | The method described in the patent application addresses the following problems in semiconductor device manufacturing:
| |
| − |
| |
| − | * Contamination on the metal layer's surface needs to be removed before further processing.
| |
| − | * The metal layer needs to be selectively removed without damaging other components.
| |
| − | * Efficient cleaning processes are required to ensure the quality and reliability of the semiconductor device.
| |
| − |
| |
| − | == Benefits ==
| |
| − | The use of this method offers several benefits in semiconductor device manufacturing:
| |
| − |
| |
| − | * Effective cleaning of the metal layer's surface, ensuring proper adhesion and compatibility with subsequent layers.
| |
| − | * Selective removal of the metal layer, avoiding damage to other components.
| |
| − | * Improved efficiency and reliability of the semiconductor device manufacturing process.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of forming a semiconductor device includes the following steps. A metal layer with at least one silicon-containing pattern therein is provided. A first wet etching process is performed by using a first etching solution, to clean a surface of the metal layer, wherein the first etching solution contains a base and a first oxidant. At least one cycle is performed. Each cycle includes a second wet etching process and a cleaning process. The second wet etching process is performed by using a second etching solution, to remove the metal layer, wherein the second etching solution contains an acid and a second oxidant. A cleaning process is performed.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME ([[17849739. SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849739]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME ([[17849739. SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849739]])=== |
| Line 1,015: |
Line 295: |
| | Chia-Hao Chang | | Chia-Hao Chang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device that includes a substrate, stacks of semiconductor nanosheets, a gate structure, strained layers, and a blocking wall. Here are the key points:
| |
| − |
| |
| − | * The device has a substrate with two fins separated by an insulating region.
| |
| − | * Semiconductor nanosheets are arranged in two stacks, one on each fin.
| |
| − | * The gate structure wraps around the nanosheet stacks.
| |
| − | * Strained layers are placed on each fin, adjacent to the respective nanosheet stack.
| |
| − | * A blocking wall is positioned on the insulating region, between the strained layers.
| |
| − | * The top surface of the blocking wall is higher than the top surface of the strained layers.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Advanced semiconductor devices for various electronic applications.
| |
| − | * Improved performance and efficiency in electronic devices.
| |
| − | * Enhanced integration of nanosheet technology in semiconductor manufacturing.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a structure that allows for better control and manipulation of semiconductor nanosheets.
| |
| − | * Addresses challenges in integrating nanosheet technology with existing semiconductor processes.
| |
| − | * Offers improved performance and functionality in electronic devices.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Enables the development of more advanced and efficient electronic devices.
| |
| − | * Enhances the performance and capabilities of semiconductor nanosheets.
| |
| − | * Provides a solution for integrating nanosheet technology into existing semiconductor manufacturing processes.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a substrate, first and second stacks of semiconductor nanosheets, a gate structure, first and second strained layers and a blocking wall. The substrate includes first and second fins separated by an insulating region. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets disposed on the second fin. The gate structure wraps the first and second stacks of semiconductor nanosheets. The first strained layer is disposed on the first fin adjacent to the first stack of semiconductor nanosheets. The second strained layer is disposed on the second fin adjacent to the second stack of semiconductor nanosheets. The blocking wall is disposed on the insulating region and located between the first and second strained layers. The top surface of the blocking wall is higher than the top surface of the first strained layer or the second strained layer.
| |
| | | | |
| | ===INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS ([[17850811. INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850811]])=== | | ===INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS ([[17850811. INTEGRATED CIRCUIT WITH BOTTOM DIELECTRIC INSULATORS AND FIN SIDEWALL SPACERS FOR REDUCING SOURCE/DRAIN LEAKAGE CURRENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850811]])=== |
| Line 1,054: |
Line 303: |
| | Jung-Hung CHANG | | Jung-Hung CHANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes an integrated circuit that includes a nanostructure transistor with semiconductor nanostructures and a source/drain region. The circuit also includes a fin sidewall spacer and a bottom isolation structure.
| |
| − |
| |
| − | * The integrated circuit includes a nanostructure transistor with multiple semiconductor nanostructures and a source/drain region.
| |
| − | * A fin sidewall spacer is used to laterally bound a lower portion of the source/drain region.
| |
| − | * A bottom isolation structure is included to electrically isolate the source/drain region from the semiconductor substrate.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in various electronic devices that require integrated circuits, such as smartphones, computers, and IoT devices.
| |
| − | * It can be applied in the development of advanced processors, memory chips, and other high-performance computing components.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The integration of nanostructure transistors with semiconductor nanostructures helps to improve the performance and efficiency of integrated circuits.
| |
| − | * The use of a fin sidewall spacer and bottom isolation structure helps to enhance the electrical isolation and reduce leakage current in the circuit.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The integrated circuit with nanostructure transistors provides improved performance and efficiency compared to traditional transistors.
| |
| − | * The use of fin sidewall spacers and bottom isolation structures helps to minimize electrical interference and leakage, leading to better overall circuit performance.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An integrated circuit includes a nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source/drain region in contact with each of the semiconductor nanostructures. The integrated circuit includes a fin sidewall spacer laterally bounding a lower portion of the source/drain region. The integrated circuit also includes a bottom isolation structure electrically isolating the source/drain region from the semiconductor substrate.
| |
| | | | |
| | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[18464839. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18464839]])=== | | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[18464839. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18464839]])=== |
| Line 1,084: |
Line 311: |
| | Ka-Hing FUNG | | Ka-Hing FUNG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor structure that includes multiple vertically stacked and separated nanostructures, an adjacent source/drain feature, and an inner spacer layer. The inner spacer layer has a vertical portion between the nanostructures and the source/drain feature, as well as horizontal portions between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer, spaced apart from the nanostructures.
| |
| − |
| |
| − | * The semiconductor structure includes vertically stacked and separated nanostructures.
| |
| − | * An inner spacer layer is present, with a vertical portion between the nanostructures and a source/drain feature.
| |
| − | * The inner spacer layer also has horizontal portions between the nanostructures.
| |
| − | * A source/drain junction is located in the vertical portion of the inner spacer layer, spaced apart from the nanostructures.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * This semiconductor structure can be used in various electronic devices such as transistors, integrated circuits, and memory devices.
| |
| − | * It can be applied in the development of high-performance and energy-efficient electronic devices.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * The structure addresses the challenge of reducing the size of electronic components while maintaining their functionality and performance.
| |
| − | * It solves the problem of minimizing interference between the nanostructures and the source/drain feature.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * The vertically stacked and separated nanostructures allow for increased device density and improved performance.
| |
| − | * The inner spacer layer provides better control over the source/drain junction and reduces interference.
| |
| − | * The semiconductor structure enables the development of smaller, more efficient, and higher-performing electronic devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another, a source/drain feature adjacent to the plurality of nanostructures, and an inner spacer layer. The inner spacer layer includes a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.
| |
| | | | |
| | ===Transistor Source/Drain Regions and Methods of Forming the Same ([[18150524. Transistor Source/Drain Regions and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18150524]])=== | | ===Transistor Source/Drain Regions and Methods of Forming the Same ([[18150524. Transistor Source/Drain Regions and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18150524]])=== |
| Line 1,116: |
Line 319: |
| | Tsung-Han Chuang | | Tsung-Han Chuang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a device that includes nanostructures, a semiconductor layer, a spacer, source/drain regions, and a gate structure. Here is a simplified explanation of the abstract:
| |
| − |
| |
| − | * The device consists of nanostructures, which are very small structures.
| |
| − | * There is a semiconductor layer that is not doped (undoped) and it contacts a dummy region of the nanostructures.
| |
| − | * A spacer is present on top of the undoped semiconductor layer.
| |
| − | * Source/drain regions are located on top of the spacer and they make contact with a channel region of the nanostructures.
| |
| − | * A gate structure is wrapped around both the channel region and the dummy region of the nanostructures.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * This device could be used in electronic devices such as transistors or integrated circuits.
| |
| − | * It may find applications in nanotechnology and semiconductor industries.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * The device provides a way to control the flow of electric current in nanostructures.
| |
| − | * It allows for efficient and precise manipulation of electronic signals.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * The device offers improved performance and functionality in electronic devices.
| |
| − | * It enables miniaturization and integration of electronic components.
| |
| − | * It may lead to advancements in nanotechnology and semiconductor industries.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | In an embodiment, a device includes: first nanostructures; a first undoped semiconductor layer contacting a first dummy region of the first nanostructures; a first spacer on the first undoped semiconductor layer; a first source/drain region on the first spacer, the first source/drain region contacting a first channel region of the first nanostructures; and a first gate structure wrapped around the first channel region and the first dummy region of the first nanostructures.
| |
| | | | |
| | ===METHOD FOR FORMING SEMICONDUCTOR DEVICE ([[17849734. METHOD FOR FORMING SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849734]])=== | | ===METHOD FOR FORMING SEMICONDUCTOR DEVICE ([[17849734. METHOD FOR FORMING SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849734]])=== |
| Line 1,152: |
Line 327: |
| | Sheng-Tsung Wang | | Sheng-Tsung Wang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for forming a semiconductor device. Here are the key points:
| |
| − |
| |
| − | * A transistor is formed and embedded in a dielectric layer over a semiconductor substrate.
| |
| − | * A first gate cutting process is performed to create an opening in the dielectric layer.
| |
| − | * An insulator post is formed in the opening.
| |
| − | * A second gate cutting process is performed to create another opening in the dielectric layer.
| |
| − | * A power via is formed in the second opening.
| |
| − | * A conductor is formed and embedded in the semiconductor substrate, located under and electrically connected to the power via.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | This technology can be applied in various semiconductor devices, including but not limited to:
| |
| − |
| |
| − | * Integrated circuits
| |
| − | * Microprocessors
| |
| − | * Memory devices
| |
| − | * Power management systems
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | The method described in the patent application addresses the following problems:
| |
| − |
| |
| − | * Efficiently embedding a transistor in a dielectric layer over a semiconductor substrate.
| |
| − | * Creating openings in the dielectric layer for insulator posts and power vias.
| |
| − | * Ensuring proper electrical connection between the conductor and the power via.
| |
| − |
| |
| − | == Benefits ==
| |
| − | The use of this technology offers several benefits:
| |
| − |
| |
| − | * Improved integration of transistors in semiconductor devices.
| |
| − | * Enhanced power management capabilities.
| |
| − | * Increased efficiency and performance of the semiconductor device.
| |
| − | * Potential for miniaturization and cost reduction in semiconductor manufacturing.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for forming a semiconductor device includes followings. A transistor is formed, and the transistor is embedded in a dielectric layer and disposed over a semiconductor substrate. A first gate cutting process is performed to form a first opening in the dielectric layer. An insulator post is formed in the first opening. A second gate cutting process is performed to form a second opening in the dielectric layer. A power via is formed in the second opening. A conductor is formed, wherein the conductor is embedded in the semiconductor substrate, and the conductor is located under and electrically connected to the power via.
| |
| | | | |
| | ===INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF ([[17850845. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850845]])=== | | ===INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF ([[17850845. INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17850845]])=== |
| Line 1,196: |
Line 335: |
| | Yi-Ruei JHAN | | Yi-Ruei JHAN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a method of manufacturing an integrated circuit device. Here is a simplified explanation of the abstract:
| |
| − |
| |
| − | * The method starts by forming a semiconductor fin on a semiconductor substrate.
| |
| − | * An isolation structure is then formed around the semiconductor fin to provide electrical isolation.
| |
| − | * A trench is etched in the semiconductor fin.
| |
| − | * A dielectric fin is formed in the trench.
| |
| − | * After forming the dielectric fin, the top surface of the isolation structure is recessed.
| |
| − | * This recess allows the dielectric fin and the semiconductor fin to protrude from the top surface of the isolation structure.
| |
| − | * Finally, a first metal gate structure and a second metal gate structure are formed over the dielectric fin and the semiconductor fin, respectively.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Manufacturing of integrated circuit devices, such as microprocessors, memory chips, and other electronic components.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for forming a dielectric fin in a semiconductor fin, allowing for improved performance and functionality of integrated circuit devices.
| |
| − | * Enables the formation of metal gate structures over the dielectric fin and the semiconductor fin, enhancing the electrical properties of the integrated circuit device.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Improved performance and functionality of integrated circuit devices.
| |
| − | * Enhanced electrical properties, leading to better efficiency and reliability.
| |
| − | * Enables the manufacturing of more advanced and complex integrated circuit devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method of manufacturing an integrated circuit device is provided. The method includes forming a semiconductor fin over a semiconductor substrate; forming an isolation structure surrounding the semiconductor fin; etching a trench in the semiconductor fin; forming a dielectric fin in the trench; after forming the dielectric fin, recessing a top surface of the isolation structure, such that the dielectric fin and the semiconductor fin protrude from the recessed top surface of the isolation structure; and forming a first metal gate structure and a second metal gate structure over the dielectric fin and the semiconductor fin, respectively.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[18153491. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18153491]])=== | | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[18153491. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18153491]])=== |
| Line 1,233: |
Line 343: |
| | Chia-Ling Chung | | Chia-Ling Chung |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a semiconductor device and a method for fabricating it. The device includes a gate structure with various layers, including low-k and high-k dielectric layers, p-type and n-type metal layers, a silicon oxide scap layer, and a glue layer. The device also includes a continuous tungsten (W) cap formed by pretreating the gate structure, depositing and etching back W material, etching the scap layer, depositing additional W material, and removing unwanted W material. The fabrication method involves receiving a gate structure, pretreating it, depositing W material, etching back the W material, etching the scap layer, depositing additional W material, and removing unwanted W material.
| |
| − |
| |
| − | * The semiconductor device includes a gate structure with multiple layers and a tungsten cap.
| |
| − | * The fabrication method involves pretreating the gate structure, depositing and etching back tungsten material, etching the scap layer, depositing additional tungsten material, and removing unwanted tungsten material.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This technology can be used in the fabrication of semiconductor devices, such as integrated circuits.
| |
| − | * It can be applied in various industries that utilize semiconductor devices, including electronics, telecommunications, and computing.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The disclosed semiconductor device and fabrication method address the need for a reliable and efficient gate structure in semiconductor devices.
| |
| − | * It solves the problem of maintaining the integrity and performance of the gate structure during fabrication and operation.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The use of a tungsten cap provides enhanced protection and stability to the gate structure.
| |
| − | * The fabrication method ensures precise deposition and removal of tungsten material, resulting in a well-defined and reliable gate structure.
| |
| − | * The combination of different layers in the gate structure improves the overall performance and efficiency of the semiconductor device.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a gate structure over a semiconductor substrate, having a low-k dielectric layer, a high-k dielectric layer, a p-type work function metal layer, an n-type work function metal layer, a silicon oxide scap layer, and a glue layer; and a continuous tungsten (W) cap over the gate structure that was formed by the gate structure being pretreated, W material being deposited and etched back, the scap layer being etched, additional W material being deposited, and unwanted W material being removed. A semiconductor fabrication method includes: receiving a gate structure; pretreating the gate structure; depositing W material on the gate structure; etching back the W material; etching the scap layer; depositing additional W material; and removing unwanted W material.
| |
| | | | |
| | ===DEVICE WITH MODIFIED WORK FUNCTION LAYER AND METHOD OF FORMING THE SAME ([[17849154. DEVICE WITH MODIFIED WORK FUNCTION LAYER AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849154]])=== | | ===DEVICE WITH MODIFIED WORK FUNCTION LAYER AND METHOD OF FORMING THE SAME ([[17849154. DEVICE WITH MODIFIED WORK FUNCTION LAYER AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849154]])=== |
| Line 1,263: |
Line 351: |
| | Yu-Chi PAN | | Yu-Chi PAN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device that includes multiple fin structures on a substrate and a work function alloy layer on each fin structure.
| |
| − |
| |
| − | * The fin structures are made up of a first fin structure and a second fin structure.
| |
| − | * The work function alloy layer has different compositions of a first element in different portions.
| |
| − | * The first portion of the work function alloy layer, which is on the first fin structure, has a different content of the first element compared to the second portion on the second fin structure.
| |
| − |
| |
| − | Potential Applications:
| |
| − |
| |
| − | * This technology can be used in the manufacturing of semiconductor devices such as transistors.
| |
| − | * It can improve the performance and efficiency of these devices by controlling the work function of the fin structures.
| |
| − |
| |
| − | Problems Solved:
| |
| − |
| |
| − | * The technology addresses the challenge of controlling the work function of fin structures in semiconductor devices.
| |
| − | * It allows for precise tuning of the work function by adjusting the composition of the work function alloy layer.
| |
| − |
| |
| − | Benefits:
| |
| − |
| |
| − | * The technology enables better control over the electrical properties of semiconductor devices.
| |
| − | * It can lead to improved device performance, power efficiency, and reliability.
| |
| − | * The ability to adjust the work function can enhance the functionality and versatility of semiconductor devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a plurality of fin structures disposed over a substrate and a work function alloy layer disposed over each fin structure of the plurality of fin structures. The plurality of fin structures includes a first fin structure and a second fin structure. A content of a first element in a first portion of the work function alloy layer, which portion is disposed over the first fin structure, is different from a content of the first element in a second portion of the work function alloy layer, which portion is disposed over the second fin structure.
| |
| | | | |
| | ===METAL LAYER PROTECTION DURING WET ETCHING ([[17809025. METAL LAYER PROTECTION DURING WET ETCHING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809025]])=== | | ===METAL LAYER PROTECTION DURING WET ETCHING ([[17809025. METAL LAYER PROTECTION DURING WET ETCHING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809025]])=== |
| Line 1,297: |
Line 359: |
| | Kuo-Ju Chen | | Kuo-Ju Chen |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method of fabricating a contact in a semiconductor device. The method involves several steps, including forming a metal layer and a bottom anti-reflective coating (BARC) layer in an opening of a semiconductor structure. Implanting operations are then performed with a dopant on the BARC layer and the metal layer to create a crust layer on top of the BARC layer. Unwanted metal layer sections are removed using wet etching operations, with the crust layer and BARC layer protecting the remaining metal layer sections. The crust layer and BARC layer are then removed, and the contact is formed in the opening over the remaining metal layer sections.
| |
| − |
| |
| − | * Metal layer and BARC layer are formed in an opening of a semiconductor structure.
| |
| − | * Implanting operations with a dopant are performed to create a crust layer on top of the BARC layer.
| |
| − | * Unwanted metal layer sections are removed using wet etching operations, with the crust layer and BARC layer protecting the remaining metal layer sections.
| |
| − | * The crust layer and BARC layer are removed.
| |
| − | * The contact is formed in the opening over the remaining metal layer sections.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − | * Semiconductor manufacturing industry
| |
| − | * Electronics industry
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − | * Protects remaining metal layer sections during wet etching operations
| |
| − | * Provides a method for fabricating a contact in a semiconductor device
| |
| − |
| |
| − | Benefits of this technology:
| |
| − | * Simplifies the process of fabricating a contact in a semiconductor device
| |
| − | * Improves the efficiency and reliability of the contact formation process
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed is a method of fabricating a contact in a semiconductor device. The method includes: receiving a semiconductor structure having an opening into which the contact is to be formed; forming a metal layer in the opening; forming a bottom anti-reflective coating (BARC) layer in the opening; performing implanting operations with a dopant on the BARC layer and the metal layer, the performing implanting operations including controlling an implant energy level and controlling an implant dosage level to form a crust layer with a desired minimum depth on top of the BARC layer; removing unwanted metal layer sections using wet etching operations, wherein the crust layer and BARC layer protect remaining metal layer sections under the BARC layer from metal loss during the wet etching operations; removing the crust layer and the BARC layer; and forming the contact in the opening over the remaining metal layer sections.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17809030. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809030]])=== | | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[17809030. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17809030]])=== |
| Line 1,329: |
Line 367: |
| | Chia-Ling Chung | | Chia-Ling Chung |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device and a method for fabricating it. The device includes a substrate with a metal gate, gate spacers, an etch stop layer, and interlayer dielectric material. It also includes a tungsten cap formed from tungsten material deposited over the metal gate and between the gate spacers. A via gate is formed above the tungsten cap.
| |
| − |
| |
| − | * The semiconductor device includes a metal gate, gate spacers, an etch stop layer, and interlayer dielectric material.
| |
| − | * A tungsten cap is formed by depositing tungsten material over the metal gate and between the gate spacers.
| |
| − | * A via gate is formed above the tungsten cap.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Semiconductor manufacturing
| |
| − | * Integrated circuits
| |
| − | * Electronics industry
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for fabricating a semiconductor device with improved performance and reliability.
| |
| − | * Helps to prevent unwanted leakage and short circuits in the device.
| |
| − | * Enhances the overall efficiency and functionality of the device.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Improved performance and reliability of semiconductor devices.
| |
| − | * Reduced risk of leakage and short circuits.
| |
| − | * Enhanced efficiency and functionality of the devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed is a semiconductor device and semiconductor fabrication method. A semiconductor device includes: a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; a tungsten (W) cap formed from W material deposited over the metal gate and between the gate spacers; and a via gate (VG) formed above the W cap. A semiconductor fabrication method includes: receiving a substrate having a metal gate, gate spacers on sides of the metal gate, an etch stop layer (ESL), and interlayer dielectric (ILD) material over a source/drain region; depositing tungsten (W) material over the substrate; removing unwanted W material to form a W cap; and forming a via gate (VG) on the W cap.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF ([[17849424. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849424]])=== | | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF ([[17849424. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849424]])=== |
| Line 1,365: |
Line 375: |
| | Wen-Yen CHEN | | Wen-Yen CHEN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device that includes a field effect transistor (FET) and a distributed Bragg reflector (DBR). The FET is placed on one side of a semiconductor substrate, while the DBR is placed on the opposite side. A conductive via passes through the substrate and makes direct electrical contact with the FET's source/drain region. A metal silicide is formed in the source/drain region to reduce contact resistance with the conductive via. The DBR helps protect other regions of the device during laser annealing of the source/drain region.
| |
| − |
| |
| − | * A semiconductor device with a field effect transistor (FET) and a distributed Bragg reflector (DBR) is described.
| |
| − | * The FET is placed on one side of a semiconductor substrate, while the DBR is placed on the opposite side.
| |
| − | * A conductive via passes through the substrate and makes direct electrical contact with the FET's source/drain region.
| |
| − | * A metal silicide is formed in the source/drain region to reduce contact resistance with the conductive via.
| |
| − | * The DBR helps protect other regions of the device during laser annealing of the source/drain region.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * This technology can be used in the manufacturing of semiconductor devices, particularly those with FETs.
| |
| − | * It can improve the performance and reliability of these devices by reducing contact resistance and preventing thermal damage.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Contact resistance between the source/drain region and the conductive via is reduced, improving the overall performance of the semiconductor device.
| |
| − | * The DBR protects other regions of the device during laser annealing, preventing thermal damage and ensuring the device's integrity.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Reduced contact resistance improves the efficiency and reliability of the semiconductor device.
| |
| − | * The DBR prevents thermal damage to other regions of the device, enhancing its overall durability and performance.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a field effect transistor disposed over a first main surface of a semiconductor substrate, a distributed Bragg reflector disposed over an opposing second main surface of the semiconductor substrate, and a conductive via disposed in the distributed Bragg reflector. The field effect transistor includes a gate structure and a source/drain region. The conductive via passes through the semiconductor substrate and is in direct electrical contact with the source/drain region. A metal silicide is formed in a portion of the source/drain region that is in contact with the conductive via, and thus can reduce contact resistance between the source/drain region and the conductive via. The source/drain region is laser annealed through an opening formed through the distributed Bragg reflector. The distributed Bragg reflector reduces or prevents thermal damage to other regions of the semiconductor device that are protected by the distributed Bragg reflector.
| |
| | | | |
| | ===METHOD FOR FORMING DUAL SILICIDE IN MANUFACTURING PROCESS OF SEMICONDUCTOR STRUCTURE ([[17847787. METHOD FOR FORMING DUAL SILICIDE IN MANUFACTURING PROCESS OF SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847787]])=== | | ===METHOD FOR FORMING DUAL SILICIDE IN MANUFACTURING PROCESS OF SEMICONDUCTOR STRUCTURE ([[17847787. METHOD FOR FORMING DUAL SILICIDE IN MANUFACTURING PROCESS OF SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847787]])=== |
| Line 1,397: |
Line 383: |
| | Ying-Chi SU | | Ying-Chi SU |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for manufacturing a semiconductor structure with different materials. The method involves forming a patterned structure with a first semiconductor portion and a second semiconductor portion. The first and second semiconductor portions are then subjected to an oxide formation process, resulting in the formation of two oxidation layers with different thicknesses.
| |
| − |
| |
| − | * The method involves forming a patterned structure with different semiconductor materials.
| |
| − | * The oxide formation process is used to oxidize the semiconductor portions.
| |
| − | * The first oxidation layer formed on the first semiconductor portion has a thickness less than that of the second oxidation layer formed on the second semiconductor portion.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Semiconductor manufacturing industry
| |
| − | * Electronics industry
| |
| − | * Integrated circuit fabrication
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Provides a method for manufacturing a semiconductor structure with different materials.
| |
| − | * Allows for the formation of oxidation layers with different thicknesses.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Enables the creation of semiconductor structures with tailored properties.
| |
| − | * Provides flexibility in designing and fabricating semiconductor devices.
| |
| − | * Offers potential improvements in performance and functionality of semiconductor devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method for manufacturing a semiconductor structure includes: forming a patterned structure which includes a first semiconductor portion and a second semiconductor portion, the first and second semiconductor portions having different materials; and performing an oxide formation process to oxidize the first and second semiconductor portions such that a first oxidation layer formed on the first semiconductor portion has a thickness less than that of a second oxidation layer formed on the second semiconductor portion.
| |
| | | | |
| | ===SEMICONDUCTOR DEVICE WITH REVERSE-CUT SOURCE/DRAIN CONTACT STRUCTURE AND METHOD THEREOF ([[17892864. SEMICONDUCTOR DEVICE WITH REVERSE-CUT SOURCE/DRAIN CONTACT STRUCTURE AND METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17892864]])=== | | ===SEMICONDUCTOR DEVICE WITH REVERSE-CUT SOURCE/DRAIN CONTACT STRUCTURE AND METHOD THEREOF ([[17892864. SEMICONDUCTOR DEVICE WITH REVERSE-CUT SOURCE/DRAIN CONTACT STRUCTURE AND METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17892864]])=== |
| Line 1,432: |
Line 391: |
| | Meng-Huan Jao | | Meng-Huan Jao |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a method for fabricating a structure with gate structures, source/drain electrodes, etch stop layers, and interlayer dielectric layers. The method involves forming trenches and depositing a dielectric layer and a metal layer into the trenches.
| |
| − |
| |
| − | * The method involves providing a structure with gate structures, source/drain electrodes, etch stop layers, and interlayer dielectric layers.
| |
| − | * A first etch mask is formed and a first etching is performed to create first trenches in the structure.
| |
| − | * A third dielectric layer is deposited into the first trenches.
| |
| − | * A second etch mask is formed and a second etching is performed to create second trenches, exposing some of the source/drain electrodes.
| |
| − | * A metal layer is deposited into the second trenches.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * This method can be used in the fabrication of semiconductor devices.
| |
| − | * It can be applied in the manufacturing of integrated circuits.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * The method solves the problem of forming trenches in a structure with gate structures and source/drain electrodes.
| |
| − | * It addresses the challenge of depositing a dielectric layer and a metal layer into the trenches.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * The method provides a simplified process for fabricating structures with trenches.
| |
| − | * It allows for the precise formation of trenches and deposition of dielectric and metal layers.
| |
| − | * The method improves the efficiency and reliability of semiconductor device manufacturing.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A method includes providing a structure having gate structures, source/drain electrodes, a first etch stop layer (ESL), a first interlayer dielectric (ILD) layer, a second ESL, and a second ILD layer. The method includes forming a first etch mask; performing a first etching to the second ILD layer, the second ESL, and the first ILD layer through the first etch mask to form first trenches; depositing a third dielectric layer into the first trenches; forming a second etch mask; and performing a second etching to the second ILD layer, the second ESL, the first ILD layer, and the first ESL through the second etch mask, thereby forming second trenches, wherein the second trenches expose some of the source/drain electrodes, and the third dielectric layer resists the second etching. The method further includes depositing a metal layer into the second trenches.
| |
| | | | |
| | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[18232526. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232526]])=== | | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[18232526. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232526]])=== |
| Line 1,465: |
Line 399: |
| | Chin-Ho Chang | | Chin-Ho Chang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a system and method for amplifying an input voltage using cascaded charge pump boosting. Here is a simplified explanation of the abstract:
| |
| − |
| |
| − | * The system stores first electrical charges at a first capacitor based on the input voltage, resulting in a second voltage.
| |
| − | * The second voltage is then amplified using the first electrical charges stored by the first capacitor, resulting in a third voltage.
| |
| − | * Second electrical charges are stored at a second capacitor based on the third voltage.
| |
| − | * Finally, the third voltage is amplified using the second electrical charges stored by the second capacitor, resulting in a fourth voltage.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Power management systems in electronic devices
| |
| − | * Voltage boosters in battery-powered devices
| |
| − | * Signal amplification in communication systems
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Efficiently amplifying an input voltage without the need for external power sources
| |
| − | * Providing a compact and cost-effective solution for voltage boosting
| |
| − | * Improving the overall performance and efficiency of electronic devices
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Increased voltage amplification without the need for additional power sources
| |
| − | * Compact and integrated design for easy implementation in various electronic devices
| |
| − | * Improved energy efficiency and longer battery life in portable devices
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Disclosed herein are related to a system and a method of amplifying an input voltage based on cascaded charge pump boosting. In one aspect, first electrical charges are stored at a first capacitor according to the input voltage to obtain a second voltage. In one aspect, the second voltage is amplified according to the first electrical charges stored by the first capacitor to obtain a third voltage. In one aspect, second electrical charges are stored at the second capacitor according to the third voltage. In one aspect, the third voltage is amplified according to the second electrical charges stored by the second capacitor to obtain a fourth voltage.
| |
| | | | |
| | ===FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES, SEMICONDUCTOR DEVICE INCLUDING SAME AND METHODS OF MANUFACTURING SAME ([[17858844. FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES, SEMICONDUCTOR DEVICE INCLUDING SAME AND METHODS OF MANUFACTURING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17858844]])=== | | ===FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES, SEMICONDUCTOR DEVICE INCLUDING SAME AND METHODS OF MANUFACTURING SAME ([[17858844. FLIP-FLOP WITH TRANSISTORS HAVING DIFFERENT THRESHOLD VOLTAGES, SEMICONDUCTOR DEVICE INCLUDING SAME AND METHODS OF MANUFACTURING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17858844]])=== |
| Line 1,502: |
Line 407: |
| | Xing Chao YIN | | Xing Chao YIN |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a semiconductor device that functions as a D flip-flop, which includes a primary latch, a secondary latch, and a clock buffer. The transistors in the device are grouped based on their threshold voltage.
| |
| − |
| |
| − | * The semiconductor device functions as a D flip-flop with a primary latch, secondary latch, and clock buffer.
| |
| − | * The transistors in the device are grouped into three categories based on their threshold voltage: standard, low, and high.
| |
| − | * The transistors in the first or second NS inverter have a low threshold voltage.
| |
| − | * The device can also function as a scan-insertion type of D flip-flop with a multiplexer, where the transistors in the multiplexer have a low threshold voltage.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * Integrated circuits and microprocessors
| |
| − | * Digital logic circuits
| |
| − | * Memory devices
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Improved performance and reliability of D flip-flops
| |
| − | * Efficient use of transistors with different threshold voltages
| |
| − | * Enhanced functionality and flexibility in circuit design
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Higher speed and lower power consumption in semiconductor devices
| |
| − | * Improved stability and robustness of D flip-flops
| |
| − | * Simplified circuit design and layout
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes: a cell region including active regions where components of transistors are formed; the cell region are arranged to function as a D flip-flop that includes a primary latch (having a first sleepy inverter and a first non-sleepy (NS) inverter), a secondary latch (having a second sleepy inverter and a second NS inverter), and a clock buffer (having third and fourth NS inverters). The transistors are grouped: a first group has a standard threshold voltage (Vt_std); a second group has a low threshold voltage (Vt_low); and an optional third group has a high threshold voltage (Vt_high). The transistors which comprise the first or second NS inverter have Vt_low. Alternatively, the transistors of the cell region are further arranged to function as a scan-insertion type of D flip-flop (SDFQ) that further includes a multiplexer; and the transistors of the multiplexer have Vt_low.
| |
| | | | |
| | ===Pipelined Hybrid Noise-Shaping Analog-To-Digital Converter ([[17847302. Pipelined Hybrid Noise-Shaping Analog-To-Digital Converter simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847302]])=== | | ===Pipelined Hybrid Noise-Shaping Analog-To-Digital Converter ([[17847302. Pipelined Hybrid Noise-Shaping Analog-To-Digital Converter simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17847302]])=== |
| Line 1,539: |
Line 415: |
| | Martin Kinyua | | Martin Kinyua |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a system and method for implementing an analog-to-digital converter (ADC) with improved accuracy and noise cancellation capabilities.
| |
| − |
| |
| − | * The ADC consists of a first-stage quantizer, a second-stage quantizer, and a noise cancellation filter.
| |
| − | * The first-stage quantizer takes in an analog input signal and generates a digital output signal, as well as a residual signal based on the input and output signals.
| |
| − | * The second-stage quantizer receives the residual signal, determines the first-stage quantization error, digitizes it, and generates a second-stage digital output signal.
| |
| − | * The noise cancellation filter takes both the first-stage and second-stage digital output signals and produces a noise-cancellation output signal that reduces the first-stage quantization error.
| |
| − |
| |
| − | Potential applications of this technology:
| |
| − |
| |
| − | * High-precision measurement devices that require accurate conversion of analog signals to digital format.
| |
| − | * Audio and video recording equipment that needs to capture and digitize analog signals with minimal noise and distortion.
| |
| − | * Communication systems that rely on ADCs for converting analog signals to digital for transmission and processing.
| |
| − |
| |
| − | Problems solved by this technology:
| |
| − |
| |
| − | * Improved accuracy in analog-to-digital conversion by reducing quantization errors introduced at each stage of the conversion process.
| |
| − | * Enhanced noise cancellation capabilities to minimize the impact of quantization errors on the final digital output signal.
| |
| − |
| |
| − | Benefits of this technology:
| |
| − |
| |
| − | * Higher accuracy and precision in converting analog signals to digital format.
| |
| − | * Reduced noise and distortion in the digitized signals.
| |
| − | * Improved signal-to-noise ratio, leading to better overall performance in various applications.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Systems and methods are provided for implementing an analog-to-digital converter. In some embodiments, the analog-to-digital converter comprises a first-stage quantizer, a second-stage quantizer, and a noise cancellation filter. The first-stage quantizer is configured to receive an analog input signal and generate a first-stage digital output signal based on the analog input signal and a residual signal based on the first-stage digital output signal and the analog input signal. The second-stage quantizer is configured to receive the residual signal, to determine a first-stage quantization error based on the residual signal, to digitize the first-stage quantization error, and to generate a second-stage digital output signal based on the first-stage quantization error. The noise cancellation filter is configured to receive the first-stage digital output signal and the second-stage digital output signal and to generate a noise-cancellation output signal comprising a quantization error component less that the first-stage quantization error.
| |
| | | | |
| | ===ELECTRIC DEVICE, ITS CIRCUIT BOARD AND METHOD OF MANUFACTURING THE ELECTRIC DEVICE ([[17818722. ELECTRIC DEVICE, ITS CIRCUIT BOARD AND METHOD OF MANUFACTURING THE ELECTRIC DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17818722]])=== | | ===ELECTRIC DEVICE, ITS CIRCUIT BOARD AND METHOD OF MANUFACTURING THE ELECTRIC DEVICE ([[17818722. ELECTRIC DEVICE, ITS CIRCUIT BOARD AND METHOD OF MANUFACTURING THE ELECTRIC DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17818722]])=== |
| Line 1,575: |
Line 423: |
| | Chih-Chieh LIAO | | Chih-Chieh LIAO |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes an electric device that includes a semiconductor assembly, a circuit board, and two types of conductive pads. The circuit board has a rectangular chip-mounted area. The first conductive pads are located in the center zone or all corner zones of the chip-mounted area, while the second conductive pads are located in the remaining area. The first conductive pads are soldered to one part of the semiconductor assembly through first solder-ball portions, and the second conductive pads are soldered to another part of the semiconductor assembly through second solder-ball portions. The second conductive pads are smaller in size than the first conductive pads, and the second solder-ball portions have a greater maximum width than the first solder-ball portions.
| |
| − |
| |
| − | * The electric device includes a semiconductor assembly, a circuit board, and two types of conductive pads.
| |
| − | * The circuit board has a rectangular chip-mounted area.
| |
| − | * The first conductive pads are located in the center zone or all corner zones of the chip-mounted area.
| |
| − | * The second conductive pads are located in the remaining area of the chip-mounted area.
| |
| − | * The first conductive pads are soldered to one part of the semiconductor assembly through first solder-ball portions.
| |
| − | * The second conductive pads are soldered to another part of the semiconductor assembly through second solder-ball portions.
| |
| − | * The second conductive pads are smaller in size than the first conductive pads.
| |
| − | * The second solder-ball portions have a greater maximum width than the first solder-ball portions.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Electric devices with improved semiconductor assembly connections.
| |
| − | * Circuit boards with optimized layout for efficient soldering.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Provides a more efficient and reliable connection between the semiconductor assembly and the circuit board.
| |
| − | * Allows for better utilization of space on the circuit board.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Enhanced performance and reliability of electric devices.
| |
| − | * Improved manufacturing process for circuit boards.
| |
| − | * Cost-effective solution for semiconductor assembly connections.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An electric device includes a semiconductor assembly, a circuit board, first conductive pads and second conductive pads. The circuit board has a chip-mounted area with a rectangular shape. The first conductive pads are arranged in a center zone or all corner zones of the chip-mounted area, and the second conductive pads are arranged within the rest in the chip-mounted area. The first conductive pads are respectively soldered to one part of solder joints of the semiconductor assembly through first solder-ball portions, and the second conductive pads are respectively soldered to another part of the solder joints of the semiconductor assembly through second solder-ball portions. Each of the second conductive pads is sized smaller than one of the first conductive pads, and a maximum width of each of the second solder-ball portions is greater than a maximum width of each of the first solder-ball portions.
| |
| | | | |
| | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[18169563. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18169563]])=== | | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[18169563. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18169563]])=== |
| Line 1,611: |
Line 431: |
| | Meng-Han Lin | | Meng-Han Lin |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | ==Abstract==
| |
| − | A semiconductor device is described in this patent application. The device consists of several components including a word line (WL) structure, a ferroelectric layer, a channel layer, a source line (SL) structure, a bit line (BL) structure, and a dielectric layer.
| |
| − |
| |
| − | * The device includes a word line (WL) structure.
| |
| − | * A ferroelectric layer is placed over the WL structure.
| |
| − | * A channel layer is placed over the ferroelectric layer.
| |
| − | * A source line (SL) structure is placed over the channel layer.
| |
| − | * A bit line (BL) structure is placed over the channel layer, with a portion extending laterally towards the SL structure.
| |
| − | * A dielectric layer is placed laterally between the SL structure and the BL structure.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Memory devices
| |
| − | * Logic devices
| |
| − | * Data storage devices
| |
| − | * Integrated circuits
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Improved performance and reliability of semiconductor devices
| |
| − | * Enhanced memory storage capabilities
| |
| − | * Increased data processing speed
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Higher density of memory storage
| |
| − | * Faster data processing
| |
| − | * Improved device performance and reliability
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A semiconductor device includes a word line (WL) structure. The semiconductor device includes a ferroelectric layer over the WL structure. The semiconductor device includes a channel layer over the ferroelectric layer. The semiconductor device includes a source line (SL) structure over the channel layer. The semiconductor device includes a bit line (BL) structure over the channel layer. The BL structure includes a portion that laterally extends toward the SL structure. The semiconductor device further includes a dielectric layer laterally interposed between the SL structure and the BL structure.
| |
| | | | |
| | ===3D MEMORY MULTI-STACK CONNECTION METHOD ([[18362196. 3D MEMORY MULTI-STACK CONNECTION METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362196]])=== | | ===3D MEMORY MULTI-STACK CONNECTION METHOD ([[18362196. 3D MEMORY MULTI-STACK CONNECTION METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362196]])=== |
| Line 1,649: |
Line 439: |
| | Chia-En Huang | | Chia-En Huang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory device that includes a first memory array with multiple memory strings arranged in a grid-like pattern. Each memory string contains multiple memory cells stacked vertically. The device also includes multiple first conductive structures that extend vertically and have a first portion and a second portion. The first portion spans across the memory cells of a corresponding pair of memory strings, while the second portion is positioned above the first portion and extends further in at least one lateral direction.
| |
| − |
| |
| − | * The memory device has a first memory array with memory strings arranged in a grid pattern.
| |
| − | * Each memory string contains multiple memory cells stacked vertically.
| |
| − | * The device includes first conductive structures that extend vertically.
| |
| − | * Each first conductive structure has a first portion and a second portion.
| |
| − | * The first portion spans across the memory cells of a corresponding pair of memory strings.
| |
| − | * The second portion is positioned above the first portion and extends further in at least one lateral direction.
| |
| − |
| |
| − | Potential Applications:
| |
| − |
| |
| − | * This memory device can be used in various electronic devices, such as smartphones, tablets, and computers.
| |
| − | * It can be utilized in data storage systems, allowing for efficient and compact memory storage.
| |
| − | * The device can be integrated into artificial intelligence systems, enabling faster processing and data retrieval.
| |
| − |
| |
| − | Problems Solved:
| |
| − |
| |
| − | * The memory device solves the problem of limited memory capacity by utilizing a grid-like arrangement of memory strings.
| |
| − | * It addresses the need for compact memory storage by stacking multiple memory cells vertically.
| |
| − | * The device solves the challenge of efficient data retrieval by using first conductive structures that span across memory cells.
| |
| − |
| |
| − | Benefits:
| |
| − |
| |
| − | * The memory device offers increased memory capacity due to the grid-like arrangement and vertical stacking of memory cells.
| |
| − | * It provides faster data retrieval and processing capabilities through the use of first conductive structures.
| |
| − | * The device allows for more compact memory storage, resulting in smaller and more efficient electronic devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory device includes a first memory array including: a plurality of memory strings spaced from each other along a first lateral direction and a second lateral direction, each of the plurality of memory strings including a plurality of memory cells arranged along a vertical direction; and a plurality of first conductive structures extending along the vertical direction; wherein each of the plurality of first conductive structures includes a first portion and a second portion; wherein the first portion extends across the plurality of memory cells of a corresponding pair of the plurality of memory strings along the vertical direction, and the second portion is disposed over the first portion along the vertical direction; and wherein the second portion extends farther than the first portion along at least one of the first or second lateral direction.
| |
| | | | |
| | ===FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME ([[17849608. FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849608]])=== | | ===FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME ([[17849608. FERROELECTRIC DEVICE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17849608]])=== |
| Line 1,688: |
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| | Hung-Wei LI | | Hung-Wei LI |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a memory device and methods of forming it. The memory device includes a gate electrode, a ferroelectric dielectric layer, a metal oxide semiconductor layer, a source feature, and a source extension. The source extension has a larger dimension than the source feature and extends downwardly from it.
| |
| − |
| |
| − | * The memory device includes a gate electrode, ferroelectric dielectric layer, metal oxide semiconductor layer, source feature, and source extension.
| |
| − | * The source extension has a larger dimension than the source feature.
| |
| − | * The source extension extends downwardly from the source feature to a lower elevation.
| |
| − | * The memory device is formed by disposing the gate electrode in an insulating material layer, placing the ferroelectric dielectric layer over the gate electrode, adding the metal oxide semiconductor layer, and then adding the source feature and source extension.
| |
| − |
| |
| − | == Potential Applications ==
| |
| − | * Memory devices for electronic devices such as computers, smartphones, and tablets.
| |
| − | * Non-volatile memory for data storage.
| |
| − | * High-density memory for increased storage capacity.
| |
| − |
| |
| − | == Problems Solved ==
| |
| − | * Provides a memory device with improved performance and reliability.
| |
| − | * Allows for increased storage capacity in memory devices.
| |
| − | * Enhances the functionality of electronic devices by providing efficient memory storage.
| |
| − |
| |
| − | == Benefits ==
| |
| − | * Improved performance and reliability of memory devices.
| |
| − | * Increased storage capacity for data storage.
| |
| − | * Enhanced functionality of electronic devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | Various embodiments of the present disclosure provide a memory device and methods of forming the same. In one embodiment, a memory device is provided. The memory device includes a gate electrode disposed in an insulating material layer, a ferroelectric dielectric layer disposed over the gate electrode, a metal oxide semiconductor layer disposed over the ferroelectric dielectric layer, a source feature disposed over the metal oxide semiconductor layer, wherein the source feature has a first dimension, and a source extension. The source extension includes a first portion disposed over the source feature, wherein the first portion has a second dimension that is greater than the first dimension. The source extension also includes a second portion extending downwardly from the first portion to an elevation that is lower than a top surface of the source feature.
| |
| | | | |
| | ===INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME ([[17848806. INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848806]])=== | | ===INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME ([[17848806. INTEGRATED CIRCUIT DEVICE AND METHOD FOR FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17848806]])=== |
| Line 1,722: |
Line 455: |
| | Kuo-Yu HSIANG | | Kuo-Yu HSIANG |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | '''Abstract:'''
| |
| − | An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.
| |
| − |
| |
| − | '''Patent/Innovation Explanation:'''
| |
| − | * The patent describes an integrated circuit device that includes a memory device.
| |
| − | * The memory device is positioned over a substrate.
| |
| − | * The memory device consists of several layers: a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode.
| |
| − | * The dielectric layer is located above the bottom electrode.
| |
| − | * The antiferroelectric layer is positioned above the dielectric layer.
| |
| − | * The top electrode is placed over the antiferroelectric layer.
| |
| − |
| |
| − | '''Potential Applications:'''
| |
| − | * This technology can be used in various electronic devices that require memory storage, such as computers, smartphones, and tablets.
| |
| − | * It can also be applied in embedded systems, automotive electronics, and IoT devices.
| |
| − |
| |
| − | '''Problems Solved:'''
| |
| − | * The patent addresses the need for an integrated circuit device with an efficient and reliable memory device.
| |
| − | * It solves the problem of storing and retrieving data in electronic devices by providing a memory device with improved performance and stability.
| |
| − |
| |
| − | '''Benefits of this Technology:'''
| |
| − | * The integrated circuit device offers enhanced memory capabilities, allowing for efficient data storage and retrieval.
| |
| − | * The technology provides improved stability and reliability in memory operations.
| |
| − | * It offers a compact and cost-effective solution for memory storage in electronic devices.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | An integrated circuit device includes a substrate and a memory device. The memory device is over the substrate. The memory device includes a bottom electrode, a dielectric layer, an antiferroelectric layer, and a top electrode. The dielectric layer is over the bottom electrode. The antiferroelectric layer is over the dielectric layer. The top electrode is over the antiferroelectric layer.
| |
| | | | |
| | ===MEMORY DEVICE ([[18152122. MEMORY DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18152122]])=== | | ===MEMORY DEVICE ([[18152122. MEMORY DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18152122]])=== |
| Line 1,758: |
Line 463: |
| | Elia Ambrosi | | Elia Ambrosi |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | ==Abstract==
| |
| − | A memory device is described in this patent application. The device consists of memory cells, each containing a resistance variable storage device and a selector. The selector is stacked on top of the storage device and connected to it through a shared terminal. The selector includes a switching layer made of a chalcogenide compound, with a thickness of 5 nm or less.
| |
| − |
| |
| − | ==Bullet Points==
| |
| − | * Memory device with memory cells
| |
| − | * Each cell has a resistance variable storage device and a selector
| |
| − | * Selector is stacked on top of the storage device and connected through a shared terminal
| |
| − | * Selector includes a switching layer made of a chalcogenide compound
| |
| − | * Thickness of the switching layer is 5 nm or less
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Computer memory systems
| |
| − | * Data storage devices
| |
| − | * Solid-state drives (SSDs)
| |
| − | * Internet of Things (IoT) devices
| |
| − | * Wearable technology
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Improved memory cell design
| |
| − | * Enhanced performance and reliability of memory devices
| |
| − | * Increased data storage capacity
| |
| − | * Reduced power consumption
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Higher data storage density
| |
| − | * Faster read and write speeds
| |
| − | * Lower power consumption
| |
| − | * Improved durability and reliability of memory devices
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A memory device is provided. The memory device includes memory cells. Each of the memory cells includes: a resistance variable storage device; and a selector. The selector is stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and includes a switching layer formed of a chalcogenide compound. A thickness of the switching layer is equal to or less than about 5 nm.
| |
| | | | |
| | ===PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHING DEVICE WITH AIR GAP ([[17851026. PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHING DEVICE WITH AIR GAP simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851026]])=== | | ===PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHING DEVICE WITH AIR GAP ([[17851026. PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHING DEVICE WITH AIR GAP simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851026]])=== |
| Line 1,799: |
Line 471: |
| | Kuo-Pin Chang | | Kuo-Pin Chang |
| | | | |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The patent application describes a phase-change material (PCM) switching device that includes a base dielectric layer, heater elements, metal pads, and a PCM region. The PCM region can switch between an amorphous state and a crystalline state in response to heat generated by the heater elements. An air gap surrounds the heater elements from three sides.
| |
| − |
| |
| − | * The device includes a base dielectric layer and a semiconductor substrate.
| |
| − | * There are two heater elements: a first heater element made of a metal with a certain coefficient of thermal expansion (CTE), and a second heater element made of a metal with a larger CTE.
| |
| − | * The PCM region, which contains the phase-change material, is located above the second heater element.
| |
| − | * The PCM can switch between an amorphous state and a crystalline state when heated by the first and second heater elements.
| |
| − | * An air gap surrounds the heater elements from three sides.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Data storage: The PCM switching device can be used in non-volatile memory applications, such as phase-change random access memory (PCRAM).
| |
| − | * Logic circuits: The device can be integrated into logic circuits to enable reconfigurable computing and programmable logic.
| |
| − | * Neuromorphic computing: The PCM switching device can be used in neuromorphic computing systems to mimic the behavior of biological neural networks.
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Limited scalability: The PCM switching device addresses the scalability issue in conventional memory technologies by providing a compact and efficient solution.
| |
| − | * High power consumption: The device offers lower power consumption compared to traditional memory technologies, making it more energy-efficient.
| |
| − | * Limited endurance: The PCM switching device provides improved endurance, allowing for a higher number of read/write cycles.
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Compact design: The device has a small footprint, making it suitable for integration into various electronic systems.
| |
| − | * Low power consumption: The PCM switching device offers energy-efficient operation, reducing power requirements.
| |
| − | * High endurance: The device has improved endurance, enabling a longer lifespan and increased reliability.
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A phase-change material (PCM) switching device includes: a base dielectric layer over a semiconductor substrate; a first heater element disposed on the base dielectric layer, the first heater element comprising a first metal element characterized by a first coefficient of thermal expansion (CTE); a second heater element disposed on the first heater element, the second heater element comprising a second metal element characterized by a second CTE larger than the first CTE; a first metal pad and a second metal pad; and a PCM region comprising a PCM operable to switch between an amorphous state and a crystalline state in response to heat generated by the first heater element and the second heater element, wherein the PCM region is disposed above a top surface of the second heater element, and an air gap surrounds the first heater element and the second heater element from three sides.
| |
| | | | |
| | ===VERTICAL PHASE CHANGE SWITCH DEVICES AND METHODS ([[17851036. VERTICAL PHASE CHANGE SWITCH DEVICES AND METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851036]])=== | | ===VERTICAL PHASE CHANGE SWITCH DEVICES AND METHODS ([[17851036. VERTICAL PHASE CHANGE SWITCH DEVICES AND METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17851036]])=== |
| Line 1,833: |
Line 478: |
| | | | |
| | Kuo-Pin Chang | | Kuo-Pin Chang |
| − |
| |
| − |
| |
| − | '''Brief explanation'''
| |
| − | The abstract describes a phase change device that includes a substrate with a top surface and a heater structure on the substrate. A phase change element is placed over the heater structure, consisting of three connected portions.
| |
| − |
| |
| − | * The device is a phase change device with a substrate and a heater structure.
| |
| − | * The heater structure has first and second sidewalls on opposite sides.
| |
| − | * A phase change element is placed over the heater structure.
| |
| − | * The phase change element consists of three connected portions.
| |
| − | * The first portion is over the heater structure.
| |
| − | * The second portion is over the first sidewall of the heater structure.
| |
| − | * The third portion is over a portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.
| |
| − |
| |
| − | ==Potential Applications==
| |
| − | * Thermal management systems
| |
| − | * Heat transfer devices
| |
| − | * Cooling systems
| |
| − |
| |
| − | ==Problems Solved==
| |
| − | * Efficient heat transfer
| |
| − | * Improved thermal management
| |
| − | * Enhanced cooling capabilities
| |
| − |
| |
| − | ==Benefits==
| |
| − | * Increased heat dissipation
| |
| − | * Better temperature control
| |
| − | * Enhanced device performance
| |
| − |
| |
| − | '''Abstract'''
| |
| − | A phase change device includes a substrate with a top surface. A heater structure is disposed on the substrate. The heater structure has first and second sidewalls on opposite sides of the heater structure. A phase change element is disposed over the heater structure. The phase change element includes three connected portions. A first portion is disposed over the heater structure. A second portion is disposed over the first sidewall of the heater structure. A third portion is over a first portion of the top surface of the substrate adjacent to and spaced apart from the first sidewall of the heater structure.
| |
