18157252. DATA COMPUTATION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

DATA COMPUTATION CIRCUIT AND METHOD

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chia-Fu Lee of Hsinchu (TW)

Cheng Han Lu of Hsinchu (TW)

Yu-Der Chih of Hsinchu (TW)

Jonathan Tsung-Yung Chang of Hsinchu (TW)

Yen-Huei Chen of Hsinchu (TW)

Chen-En Lee of Hsinchu (TW)

Wei-Chang Zhao of Hsinchu (TW)

Haruki Mori of Hsinchu (TW)

Hidehiro Fujiwara of Hsinchu (TW)

DATA COMPUTATION CIRCUIT AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18157252 titled 'DATA COMPUTATION CIRCUIT AND METHOD

Simplified Explanation

The patent application describes a circuit that performs multiplication and reformatting operations on input and weight data elements. It includes a multiplier circuit, a summing circuit, a shifting circuit, and an adder tree.

• The multiplier circuit receives signed mantissas of input and weight data elements and generates two's complement products.
• The summing circuit adds the exponents of each input and weight data element to generate sums.
• The shifting circuit shifts each product based on the difference between a corresponding sum and a maximum sum.
• The adder tree generates a mantissa sum from the shifted products.

Potential applications of this technology:

• Digital signal processing
• Machine learning algorithms
• Image and video processing
• Financial modeling and analysis

Problems solved by this technology:

• Efficient multiplication and reformatting of data elements
• Accurate calculation of sums and mantissa sums
• Handling of signed mantissas and exponents

Benefits of this technology:

• Improved accuracy and precision in calculations
• Faster processing speed
• Reduced circuit complexity
• Compatibility with various applications and algorithms

Original Abstract Submitted

A circuit includes a multiplier circuit that receives a signed mantissa of each data element of pluralities of input and weight data elements and generates two's complement products by performing multiplication and reformatting operations on some or all of the input data element signed mantissas and some or all of the weight data element signed mantissas, a summing circuit that receives an exponent of each data element of the pluralities of input and weight data elements and generates sums by adding each input data element exponent to each weight data element exponent, a shifting circuit that shifts each product by an amount equal to a difference between a corresponding sum and a maximum sum, and an adder tree that generates a mantissa sum from the shifted products.