17809099. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)

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HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Wan-Jyun Syue of Hsinchu County (TW)

Hsueh-Liang Chou of Jhubei City (TW)

Yi-Jen Lo of Hsinchu City (TW)

HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION - A simplified explanation of the abstract

This abstract first appeared for US patent application 17809099 titled 'HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION

Simplified Explanation

The abstract describes a high-voltage transistor design that uses planar active regions instead of fin active regions to reduce the surface area in contact with surrounding dielectric layers. This reduces charge trapping and improves performance stability and operational lifetime of the transistor.

  • The high-voltage transistor includes planar active regions for source/drain and channel regions.
  • Planar active regions replace fin active regions to minimize contact with surrounding dielectric layers.
  • This reduces the interface surface area between silicon-based active regions and oxide-based dielectric layers.
  • The reduced interface surface area decreases charge trapping in the transistor.
  • The design improves performance stability and extends the operational lifetime of the high-voltage transistor.

Potential Applications

  • High-voltage transistors used in power electronics.
  • Transistors used in electric vehicles and renewable energy systems.
  • Integrated circuits for industrial automation and control systems.

Problems Solved

  • Charge trapping in high-voltage transistors.
  • Performance instability and reduced operational lifetime.
  • Surface area contact with surrounding dielectric layers.

Benefits

  • Improved performance stability of high-voltage transistors.
  • Extended operational lifetime of high-voltage transistors.
  • Enhanced reliability and efficiency of power electronics systems.


Original Abstract Submitted

A high-voltage transistor may include a planar active region for a first source/drain active region, a second source/drain active region, and/or a channel active region. The planar active region(s) are included instead of a plurality of fin active regions to reduce the amount of surface area of the active regions in the high-voltage transistor that is in contact with surrounding dielectric layers of the high-voltage transistor. In other words, the planar active region(s) reduce the interface surface area between the silicon-based active regions of the high-voltage transistor and the surrounding oxide-based dielectric layers. The reduced interface surface area may reduce the occurrence of charge trapping in the high-voltage transistor, which may result in increased performance stability for the high-voltage transistor and/or may provide increased operational lifetime of the high-voltage transistor.

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