Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on November 9th, 2023

Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on November 9th, 2023

SLURRY ENHANCEMENT FOR POLISHING SYSTEM (18355884)

Main Inventor

Chun-Hung Liao

Brief explanation

- The patent application describes a method and apparatus for enhancing the oxidizability of a slurry used in a chemical mechanical polishing (CMP) process.

- The method involves securing a substrate onto a carrier of a polishing system. - A first slurry is dispensed onto a polishing pad of the polishing system using a feeder. - The first slurry is then enhanced to increase its oxidizability, creating a second slurry. - The substrate is polished using the second slurry in the polishing process.

Abstract

The present disclosure describes a method and an apparatus that can enhance the slurry oxidizability for a chemical mechanical polishing (CMP) process. The method can include securing a substrate onto a carrier of a polishing system. The method can further include dispensing, via a feeder of the polishing system, a first slurry towards a polishing pad of the polishing system. The method can further include forming a second slurry by enhancing an oxidizability of the first slurry, and performing a polishing process, with the second slurry, on the substrate.

Self-Aligned Acoustic Hole Formation in Piezoelectrical MEMS Microphone (17811109)

Main Inventor

Ting-Jung Chen

Brief explanation

The patent application describes a process for creating a membrane with piezoelectric layers and electrodes. 

• The process involves depositing multiple layers of piezoelectric material and electrode material.
• The electrodes are patterned to form distinct areas.
• A through-hole is created by etching the layers of piezoelectric material.
• The through-hole is positioned away from the electrodes.
• Contact plugs are formed to connect to the electrodes.

Abstract

A membrane is formed through processes including depositing a first piezoelectrical layer, depositing a first electrode layer over the first piezoelectrical layer, patterning the first electrode layer to form a first electrode, depositing a second piezoelectrical layer over the first electrode, depositing a second electrode layer over the second piezoelectrical layer, patterning the second electrode layer to form a second electrode, and depositing a third piezoelectrical layer over the second electrode. The third piezoelectrical layer, the second piezoelectrical layer, and the first piezoelectrical layer are etched to form a through-hole. The through-hole is laterally spaced apart from the first electrode and the second electrode. A first contact plug and a second contact plug are then formed to electrically connect to the first electrode and the second electrode, respectively.

Integrated 3DIC With Stacked Photonic Dies and Method Forming Same (18356831)

Main Inventor

Chen-Hua Yu

Brief explanation

The patent application describes a method for creating a photonic device using multiple layers of silicon and nitride waveguides.

• The method involves forming a first photonic die, which includes a silicon waveguide and a nitride waveguide.
• A through-via is created in the first photonic die, extending into multiple layers of dielectric material.
• A second photonic die is then bonded to the first photonic die, which includes a nitride waveguide.
• The silicon waveguide in the first die is optically connected to the nitride waveguide in the second die through the nitride waveguide in the first die.
• A second through-via is created in the second photonic die, extending into its own set of dielectric layers.

Abstract

A method includes forming a first photonic die, which includes forming a first silicon waveguide, and forming a first nitride waveguide. The method further includes forming a first through-via extending into a first plurality of dielectric layers in the first photonic die, and bonding a second photonic die to the first photonic die. The second photonic die includes a second nitride waveguide. The first silicon waveguide is optically coupled to the second nitride waveguide through the first nitride waveguide. A second through-via extends into a second plurality of dielectric layers in the second photonic die.

PHOTONIC DEVICE (18352727)

Main Inventor

Sui-Ying HSU

Brief explanation

The patent application describes a photonic device that includes various components such as an optical coupler, a photodetector, a waveguide structure, a metal-dielectric stack, a contact, an interlayer dielectric layer, and a protection layer.

• The device is designed to be placed over a substrate.
• The optical coupler, photodetector, and waveguide structure are all positioned on top of the substrate.
• The waveguide structure is connected laterally to the optical coupler.
• The top of the waveguide structure is lower than the top of the optical coupler.
• A metal-dielectric stack is placed over the optical coupler, photodetector, and waveguide structure.
• The metal-dielectric stack has a hole positioned above the optical coupler.
• A contact is used to connect the photodetector to the metal-dielectric stack.
• An interlayer dielectric layer is located below the metal-dielectric stack and surrounds the contact.
• A protection layer lines the hole in the metal-dielectric stack.
• The bottom surface of the protection layer is lower than the top surface of the contact.

Abstract

A photonic device includes an optical coupler, a photodetector, a waveguide structure, a metal-dielectric stack, a contact, an interlayer dielectric layer, and a protection layer. The optical coupler, the photodetector, and the waveguide structure are over a substrate. The waveguide structure is laterally connected to the optical couple. A top of the waveguide structure is lower than a top of the optical coupler. The metal-dielectric stack is over the optical coupler, the photodetector, and the waveguide structure. The metal-dielectric stack has a hole above the optical coupler. The contact connects the photodetector to the metal-dielectric stack. The interlayer dielectric layer is below the metal-dielectric stack and surrounds the contact. The protection layer lines the hole of the metal-dielectric stack. A bottom surface of the protection layer is lower than a top surface of the contact.

MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS (18222344)

Main Inventor

Hsin-Yu CHEN

Brief explanation

The patent application describes a method for creating a multifunctional collimator structure using a dielectric layer and a substrate.

• The collimator includes a dielectric layer formed over a substrate.
• The dielectric layer has a plurality of via holes arranged in an array along a lateral direction of the first surface.
• Each via hole extends through the dielectric layer and the substrate from the first surface to the second surface in a vertical direction.
• The substrate has a high impurity doping concentration and a specific thickness to enable the collimator to filter light in a range of wavelengths.

Abstract

Disclosed is a method to fabricate a multifunctional collimator structure In one embodiment, an optical collimator, includes: a dielectric layer; a substrate; and a plurality of via holes, wherein the dielectric layer is formed over the substrate, wherein the plurality of via holes are configured as an array along a lateral direction of a first surface of the dielectric layer, wherein each of the plurality of via holes extends through the dielectric layer and the substrate from the first surface of the dielectric layer to a second surface of the substrate in a vertical direction, wherein the substrate has a bulk impurity doping concentration equal to or greater than 1×10per cubic centimeter (cm) and a first thickness, and wherein the bulk impurity doping concentration and the first thickness of the substrate are configured so as to allow the optical collimator to filter light in a range of wavelengths.

MATERIALS AND METHODS FOR FORMING RESIST BOTTOM LAYER (18352556)

Main Inventor

Jing Hong Huang

Brief explanation

The patent application describes a method for forming a bottom layer on a semiconductor substrate using a polymer and two different cross-linkers.

• The first cross-linker is activated by ultraviolet (UV) radiation, while the second cross-linker is activated by heat at a specific temperature.
• The bottom layer is exposed to a UV source to activate the first cross-linker, resulting in an exposed bottom layer.
• The exposed bottom layer is then baked to activate the second cross-linker.
• This method allows for precise control over the cross-linking process, ensuring the bottom layer is properly formed.

Abstract

A method includes forming a bottom layer over a semiconductor substrate, where the bottom layer includes a polymer bonded to a first cross-linker and a second cross-linker, the first cross-linker being configured to be activated by ultraviolet (UV) radiation and the second cross-linker being configured to be activated by heat at a first temperature. The method then proceeds to exposing the bottom layer to a UV source to activate the first cross-linker, resulting in an exposed bottom layer, where the exposing activates the first cross-linker. The method further includes baking the exposed bottom layer, where the baking activates the second cross-linker.

Integrated Circuit Overlay Test Patterns And Method Thereof (18357220)

Main Inventor

Tseng Chin Lo

Brief explanation

- The patent application is about integrated circuits and methods for measuring overlap.

- The integrated circuit described in the patent includes multiple functional cells and at least one gap next to a functional cell. - Within the gap, there is a test pattern cell called the first overlay test pattern cell. - The first overlay test pattern cell contains a certain number of patterns arranged in a specific direction at a specific pitch. - The pitch of the patterns is smaller than the smallest wavelength of visible light. - The purpose of this invention is to provide a method for measuring overlap in integrated circuits using the first overlay test pattern cell.

Abstract

Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.

OVERLAY MARKS FOR REDUCING EFFECT OF BOTTOM LAYER ASYMMETRY (18356710)

Main Inventor

Hung-Chih Hsieh

Brief explanation

The patent application describes methods of creating and using an overlay mark.

• The overlay mark consists of an upper layer and a lower layer.
• The lower layer contains two sets of compound gratings, each extending in the same direction.
• The first set of compound gratings is located in one region of the overlay mark and consists of a first element and at least two second elements.
• The second set of compound gratings is located in another region of the overlay mark and consists of a third element and at least two fourth elements.
• The first set of compound gratings is a mirror image of the second set of compound gratings.

Abstract

Methods of fabricating and using an overlay mark are provided. In some embodiments, the overlay mark includes an upper layer and a lower layer disposed below the upper layer. The lower layer includes a first plurality of compound gratings extending in a first direction and disposed in a first region of the overlay mark, each of the first plurality of compound gratings including one first element and at least two second elements disposed on one side of the first element, and a second plurality of compound gratings extending the first direction and disposed in a second region of the overlay mark , each of the second plurality of compound gratings including one third element and at least two fourth elements on one side of the third element. The first plurality of compound gratings is a mirror image of the second plurality of compound gratings.

Fingerprint Sensor in InFO Structure and Formation Method (18348460)

Main Inventor

Chih-Hua Chen

Brief explanation

The patent application describes a package that includes a sensor die and an encapsulating material.

• The top surface of the encapsulating material is either at the same level or higher than the top surface of the sensor die.
• The package also includes a plurality of sensing electrodes that are higher than both the sensor die and the encapsulating material.
• These sensing electrodes are arranged in rows and columns and are electrically connected to the sensor die.
• A dielectric layer is used to cover the sensing electrodes.

Abstract

A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18352872)

Main Inventor

Zong-You LUO

Brief explanation

The patent application describes a method for forming conductive lines and magnetic tunnel junction (MTJ) stacks on a wafer.

• The method involves forming bottom conductive lines on the wafer.
• A first MTJ stack is then formed over the bottom conductive lines.
• Middle conductive lines are formed over the first MTJ stack.
• A second MTJ stack is formed over the middle conductive lines.
• Finally, top conductive lines are formed over the second MTJ stack.

Abstract

A method includes forming bottom conductive lines over a wafer. A first magnetic tunnel junction (MTJ) stack is formed over the bottom conductive lines. Middle conductive lines are formed over the first MTJ stack. A second MTJ stack is formed over the middle conductive lines. Top conductive lines are formed over the second MTJ stack.

Method of Filling Gaps with Carbon and Nitrogen Doped Film (18351064)

Main Inventor

Wan-Yi Kao

Brief explanation

- The patent application describes a method for etching a semiconductor substrate to create a trench and depositing a dielectric layer using Atomic Layer Deposition (ALD).

- The dielectric layer is formed by pulsing Hexachlorodisilane (HCD) and triethylamine onto the semiconductor substrate in a specific sequence. - The ALD cycle is followed by an anneal process on the dielectric layer. - The innovation lies in the specific combination of etching, ALD, and anneal processes to create a high-quality dielectric layer that extends into the trench.

Abstract

A method includes etching a semiconductor substrate to form a trench, and depositing a dielectric layer using an Atomic Layer Deposition (ALD) cycle. The dielectric layer extends into the trench. The ALD cycle includes pulsing Hexachlorodisilane (HCD) to the semiconductor substrate, purging the HCD, pulsing triethylamine to the semiconductor substrate, and purging the triethylamine. An anneal process is then performed on the dielectric layer.

Method of Manufacturing Semiconductor Devices (18356636)

Main Inventor

Tzu-Ang Chao

Brief explanation

- The patent application describes a semiconductor device and a method of manufacturing it using carbon nanotubes.

- The method involves forming a stack of nanotubes and then using a non-destructive removal process to reduce the thickness of the stack. - The reduced stack of nanotubes can be used to create a device, such as a transistor. - The innovation lies in the use of carbon nanotubes and the non-destructive removal process to manufacture the semiconductor device. - The method offers potential advantages in terms of performance and efficiency compared to traditional semiconductor manufacturing techniques.

Abstract

A semiconductor device and method of manufacturing using carbon nanotubes are provided. In embodiments a stack of nanotubes are formed and then a non-destructive removal process is utilized to reduce the thickness of the stack of nanotubes. A device such as a transistor may then be formed from the reduced stack of nanotubes.

Dipole-Engineered High-K Gate Dielectric and Method Forming Same (18356860)

Main Inventor

Te-Yang Lai

Brief explanation

The patent application describes a method for forming a gate electrode on a semiconductor region using high-k dielectric layers and a dipole film. 

• The method involves forming an oxide layer on the semiconductor region.
• A first high-k dielectric layer is then deposited over the oxide layer, followed by a second high-k dielectric layer.
• The second high-k dielectric layer is made of a different material than the first high-k dielectric layer.
• A dipole film is deposited and contacts either the first or second high-k dielectric layer.
• An annealing process is performed to drive-in a dipole dopant from the dipole film into the layer it contacts.
• The dipole film is then removed.
• Finally, a gate electrode is formed over the second high-k dielectric layer.

Abstract

A method includes forming an oxide layer on a semiconductor region, and depositing a first high-k dielectric layer over the oxide layer. The first high-k dielectric layer is formed of a first high-k dielectric material. The method further includes depositing a second high-k dielectric layer over the first high-k dielectric layer, wherein the second high-k dielectric layer is formed of a second high-k dielectric material different from the first high-k dielectric material, depositing a dipole film over and contacting a layer selected from the first high-k dielectric layer and the second high-k dielectric layer, performing an annealing process to drive-in a dipole dopant in the dipole film into the layer, removing the dipole film, and forming a gate electrode over the second high-k dielectric layer.

REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGES (17890980)

Main Inventor

Lung-Kun CHU

Brief explanation

The patent application describes a method for processing an integrated circuit by forming multiple transistors.

• The method involves using a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some transistors.
• This process prevents dipoles from entering the gate dielectric layers of other transistors.
• The process can be repeated to create multiple transistors with different threshold voltages.

Abstract

A method for processing an integrated circuit includes forming a plurality of transistors. The method utilizes a reversed tone patterning process to selectively drive dipoles into the gate dielectric layers of some of the transistors while preventing dipoles from entering the gate dielectric layers of other transistors. This process can be repeated to produce a plurality of transistors each having different threshold voltages.

Dielectric Gap-Filling Process for Semiconductor Device (18351985)

Main Inventor

Cheng-I Lin

Brief explanation

The patent application describes a semiconductor device and a method for its formation.

• The method involves creating a trench in a substrate.
• A liner layer is then formed along the sidewalls and bottom of the trench.
• A silicon-rich layer is formed over the liner layer.
• The silicon-rich layer is created by flowing a first silicon precursor into a process chamber for a specific time interval.
• Then, a second silicon precursor and a first oxygen precursor are flowed into the process chamber for a different time interval.
• A dielectric layer is formed over the silicon-rich layer.

Abstract

A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.

Silicon Phosphide Semiconductor Device (18354801)

Main Inventor

Tzu-Ching Lin

Brief explanation

The patent application describes a method for forming source/drain regions in a semiconductor device and a semiconductor device that includes these regions.

• The method involves etching a semiconductor fin to create a recess, with the fin having sidewalls and a bottom surface.
• A source/drain region is then formed in the recess using a single continuous material that extends from the bottom surface to above the top surface of the semiconductor fin.
• The precursor gas used for forming the source/drain region includes phosphine (PH) and either arsine (AsH) or monomethylsilane (CHSi).
• Finally, a gate is formed over the semiconductor fin adjacent to the source/drain region, with the gate extending perpendicular to the direction of the fin.

Abstract

A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH) and at least one of arsine (AsH) or monomethylsilane (CHSi); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

WAFER PROCESSING METHOD (18356084)

Main Inventor

Yan-Hong LIU

Brief explanation

The patent application describes a method for etching a wafer to remove a material from it and then performing reflectance measurements to determine if the material has been completely removed. 

• The method involves transferring the wafer from a factory interface to a load lock chamber and then to a buffer chamber.
• The wafer is then transferred to a process chamber where it is etched to remove the material.
• After the etching process, reflectance measurements are performed on the wafer in various chambers to determine if the material has been completely removed.
• The reflectance measurements can be done in the factory interface, load lock chamber, buffer chamber, or a combination of these chambers.
• The reflectance of the wafer is used as an indicator to identify if the material has been entirely removed.

Abstract

A method includes: transferring a wafer from a factory interface through a load lock chamber to a buffer chamber; transferring the wafer from the buffer chamber to a process chamber; etching the wafer in the process chamber, to remove a material of the wafer; and after the wafer is etched, performing reflectance measurements to the wafer in the factory interface, the load lock chamber, the buffer chamber, or combination thereof, to identify if the material of the wafer is removed entirely according to a reflectance of the wafer.

Passivation Structure with Planar Top Surfaces (18355799)

Main Inventor

Yi-Hsiu Chen

Brief explanation

The patent application describes a method for forming layers on a surface to reveal a metal pad.

• The method involves creating a first passivation layer on the surface.
• A metal pad is then formed over the first passivation layer.
• A planarization layer is added on top of the metal pad to create a smooth surface.
• The planarization layer is patterned to create an opening, revealing the top surface of the metal pad.
• A polymer layer is formed within the opening, extending into it.
• The polymer layer is patterned to create a second opening, again revealing the top surface of the metal pad.

Abstract

A method includes forming a first passivation layer, forming a metal pad over the first passivation layer, forming a planarization layer having a planar top surface over the metal pad, and patterning the planarization layer to form a first opening. A top surface of the metal pad is revealed through the first opening. The method further includes forming a polymer layer extending into the first opening, and patterning the polymer layer to form a second opening. The top surface of the metal pad is revealed through the second opening.

Fan-Out Package with Controllable Standoff (18351809)

Main Inventor

Po-Hao Tsai

Brief explanation

The patent application describes a method for forming an interposer, which involves creating a rigid dielectric layer and removing parts of it. 

• The interposer is then bonded to an interconnect structure, along with a package component.
• A spacer in the interposer is in contact with the package component and can be made of a metal feature, the rigid dielectric layer, or a combination of both.
• Finally, a die-saw process is performed on the interconnect structure.

Abstract

A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.

Semiconductor Device and Method of Manufacture (17819381)

Main Inventor

Chin-Yi Lin

Brief explanation

The patent application describes a semiconductor device and its manufacturing process.

• The device includes a first pad and a second pad that are located next to each other.
• A set of dummy pads is created between the first and second pads.
• Bonding pads are formed to establish electrical connections with the first and second pads.

Abstract

A semiconductor device and method of manufacture are presented in which a first pad and a second pad are formed adjacent to each other. A first set of dummy pads is manufactured between the first pad and the second pad and bonding pads are formed in electrical connection to the first pad and the second pad.

Interconnect Structure and Method of Forming Thereof (18351957)

Main Inventor

Shu-Cheng Chin

Brief explanation

The patent application describes a method for manufacturing an interconnect structure.

• The method involves creating an opening in a dielectric layer to expose a top surface of a conductive feature.
• A barrier layer is then formed on the sidewalls of the opening to protect the exposed surface.
• The top surface of the conductive feature is treated to improve its performance.
• A liner layer is applied over the barrier layer to provide additional protection.
• Finally, the opening is filled with a conductive material to complete the interconnect structure.

Abstract

A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ru

Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof (18357500)

Main Inventor

Tsung-Ling Tsai

Brief explanation

- The patent application describes a method for forming partial barrier-free vias in a multilayer interconnect structure.

- The interconnect structure includes a dielectric layer, a cobalt-comprising interconnect feature, and a partial barrier-free via. - The partial barrier-free via consists of a first via plug portion, a second via plug portion, and a via barrier layer. - The first via plug portion physically contacts both the cobalt-comprising interconnect feature and the dielectric layer. - The second via plug portion is placed over the first via plug portion, with the via barrier layer in between. - The via barrier layer is also located between the second via plug portion and the dielectric layer. - The cobalt-comprising interconnect feature can be a device-level contact or a conductive line in the multilayer interconnect structure. - The first and second via plug portions can be made of tungsten, cobalt, and/or ruthenium.

Abstract

Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Semiconductor Device with Curved Conductive Lines and Method of Forming the Same (18352595)

Main Inventor

Chia-Kuei Hsu

Brief explanation

The abstract describes a package structure for an integrated circuit die.

• The package structure includes a first integrated circuit die and a redistribution structure bonded to it.
• The redistribution structure has a first metallization pattern in a first dielectric layer, which includes multiple first conductive features.
• Each first conductive feature consists of a first conductive via in the first dielectric layer and a first conductive line over the first dielectric layer, connected to the respective first conductive via.
• The first conductive lines have a curved shape in a plan view.
• There is a second dielectric layer over the first dielectric layer and the first metallization pattern.
• The second dielectric layer contains a second metallization pattern, which includes multiple second conductive vias in the second dielectric layer.
• Each second conductive via is positioned above and electrically connected to a respective first conductive line.

Abstract

An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.

Layout Design Methodology For Stacked Devices (18224434)

Main Inventor

Fong-Yuan CHANG

Brief explanation

The patent application describes a layout design methodology for a device with multiple identical structures.

• The device consists of stacked dies, with each die having a first, second, and third layer.
• The second die includes a through-silicon via (TSV) and a circuit, while the third die includes another TSV and circuit.
• The first and second TSVs are linearly coextensive, meaning they have the same length.
• The circuits on each die are logic circuits that generate unique identifiers for the dies using comparators and counters.
• The counters of each die are connected in series between the dice.
• All the dice are manufactured using the same masks, but each retains a unique logical identifier.
• This allows for a single path in the layout to address a specific die in the stack of dice.

Abstract

A layout design methodology is provided for a device that includes two or more identical structures. Each device can have a first die, a second die stacked over the first die and a third die stacked over the second die. The second die can include a first through-silicon via (TSV) and a first circuit, and the third die can include a second TSV and a second circuit. The first TSV and the second TSV can be linearly coextensive. The first and second circuit can each be a logic circuit having a comparator and counter used to generate die identifiers. The counters of respective device die can be connected in series between the dice. Each die can be manufactured using the same masks but retain unique logical identifiers. A given die in a stack of dice can thereby be addressed by a single path in a same die layout.

BACKSIDE PN JUNCTION DIODE (18356802)

Main Inventor

Yu-Xuan Huang

Brief explanation

The present disclosure describes semiconductor devices with specific features and components. These devices include:

• An elongated semiconductor member surrounded by an isolation feature, extending in a specific direction.
• Two source/drain features located on the top surface of the elongated semiconductor member.
• A vertical stack of channel members connecting the two source/drain features along the same direction.
• A gate structure that wraps around each of the channel members.
• An epitaxial layer deposited on the bottom surface of the elongated semiconductor member.
• A silicide layer placed on top of the epitaxial layer.
• A conductive layer positioned on top of the silicide layer.

These features and components work together to create a semiconductor device with specific functionalities and performance characteristics.

Abstract

The present disclosure provides embodiments of semiconductor devices. A semiconductor device according to the present disclosure include an elongated semiconductor member surrounded by an isolation feature and extending lengthwise along a first direction, a first source/drain feature and a second source/drain feature over a top surface of the elongated semiconductor member, a vertical stack of channel members each extending lengthwise between the first source/drain feature and the second source/drain feature along the first direction, a gate structure wrapping around each of the channel members, an epitaxial layer deposited on the bottom surface of the elongated semiconductor member, a silicide layer disposed on the epitaxial layer, and a conductive layer disposed on the silicide layer.

METHOD OF FORMING A DUMMY FIN BETWEEN FIRST AND SECOND SEMICONDUCTOR FINS (18354844)

Main Inventor

Shih-Yao Lin

Brief explanation

- The patent application describes an embodiment device that includes a first source/drain region and a dummy fin adjacent to it.

- The dummy fin consists of a first portion and a second portion. - The second portion is made up of a second film and a third film, which is different from the materials used in the first film and the second film. - The width of the second portion is smaller than the width of the first portion. - The device also includes a gate stack along the sidewalls of the dummy fin.

Abstract

An embodiment device includes a first source/drain region over a semiconductor substrate and a dummy fin adjacent the first source/drain region. The dummy fin comprising: a first portion comprising a first film and a second portion over the first portion, wherein the second portion comprises: a second film; and a third film. The third film is between the first film and the second film, and the third film is made of a different material than the first film and the second film. A width of the second portion is less than a width of the first portion. The device further comprises a gate stack along sidewalls of the dummy fin.

ISOLATION STRUCTURE FOR PREVENTING UNINTENTIONAL MERGING OF EPITAXIALLY GROWN SOURCE/DRAIN (18355143)

Main Inventor

Ta-Chun Lin

Brief explanation

- The patent application describes a semiconductor device that includes two active regions and a substrate.

- The device has a first source/drain component grown on the first active region and a second source/drain component grown on the second active region. - An interlayer dielectric (ILD) is placed around both source/drain components. - An isolation structure is present within the ILD, separating the first and second source/drain components. - The purpose of the invention is to provide a structure that allows for efficient isolation of different source/drain components in a semiconductor device.

Abstract

A semiconductor device includes a first active region and a second active region disposed over a substrate. A first source/drain component is grown on the first active region. A second source/drain component is grown on the second active region. An interlayer dielectric (ILD) is disposed around the first source/drain component and the second source/drain component. An isolation structure extends vertically through the ILD. The isolation structure separates the first source/drain component from the second source/drain component.

SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW (18355211)

Main Inventor

Mrunal A. Khaderbad

Brief explanation

The patent application describes a method for selectively forming dielectric and silicide layers on different types of transistors in a semiconductor device.

• The method involves forming a first dielectric layer over the source/drain region of a first type of transistor, but not over the source/drain region of a second type of transistor.
• The first type of transistor and the second type of transistor have different types of conductivity.
• A first silicide layer is then selectively formed over the source/drain region of the second type of transistor, but not over the source/drain region of the first type of transistor.
• The first dielectric layer is removed.
• Finally, a second silicide layer is formed over the source/drain region of the first type of transistor.

Abstract

A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

2D-Channel Transistor Structure with Source-Drain Engineering (18354820)

Main Inventor

Dhanyakumar Mahaveer Sathaiya

Brief explanation

- The patent application describes a method for forming semiconductor devices using a two-dimensional (2D) material layer.

- The method involves depositing the 2D material layer over a semiconductor structure and forming a source feature and a drain feature that are electrically connected to the semiconductor structure and the 2D material layer. - The source feature and drain feature are made of a semiconductor material. - A gate structure is then formed over the 2D material layer, positioned between the source feature and the drain feature. - The combination of the gate structure, source feature, drain feature, semiconductor structure, and 2D material layer creates a field-effect transistor. - The semiconductor structure acts as the first channel, while the 2D material layer acts as the second channel between the source feature and the drain feature.

Abstract

Semiconductor devices and methods of forming the same are provided. A method includes providing a workpiece having a semiconductor structure; depositing a two-dimensional (2D) material layer over the semiconductor structure; forming a source feature and a drain feature electrically connected to the semiconductor structure and the 2D material layer, wherein the source feature and drain feature include a semiconductor material; and forming a gate structure over the two-dimensional material layer and interposed between the source feature and the drain feature. The gate structure, the source feature, the drain feature, the semiconductor structure and the 2D material layer are configured to form a field-effect transistor. The semiconductor structure and the 2D material layer function, respectively, as a first channel and a second channel between the source feature and the drain feature.

Semiconductor Device and Method of Forming the Same (18353498)

Main Inventor

Chia-Ming Chang

Brief explanation

The patent application describes a semiconductor device that includes a substrate, a semiconductor fin, and an epitaxy structure.

• The semiconductor fin is located on the substrate and has at least one recess.
• The epitaxy structure is present in the recess of the semiconductor fin.
• The epitaxy structure consists of a topmost portion, a first portion, and a second portion arranged in a specific direction.
• The first portion of the epitaxy structure has a higher percentage of germanium atoms compared to the topmost portion and the second portion.

Abstract

A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Gate Air Spacer for Fin-Like Field Effect Transistor (18355073)

Main Inventor

Chien-Ning Yao

Brief explanation

- The patent application describes gates with air gaps and methods of making them.

- The gates consist of a gate electrode and a gate dielectric. - There are two air gaps present, one between the gate electrode and the gate dielectric on the first sidewall, and another between the gate electrode and the gate dielectric on the second sidewall. - A dielectric cap is placed over the gate electrode, covering the top and filling the top portions of both air gaps. - The gates are positioned between two epitaxial source/drain regions. - The width of the gate is the same as the distance between the two epitaxial source/drain regions.

Abstract

Gates having air gaps therein, and methods of fabrication thereof, are disclosed herein. An exemplary gate includes a gate electrode and a gate dielectric. A first air gap is between and/or separates a first sidewall of the gate electrode from the gate dielectric, and a second air gap is between and/or separates a second sidewall of the gate electrode from the gate dielectric. A dielectric cap may be disposed over the gate electrode, and the dielectric cap may wrap a top of the gate electrode. The dielectric cap may fill a top portion of the first air gap and a top portion of the second air gap. The gate may be disposed between a first epitaxial source/drain and a second epitaxial source/drain, and a width of the gate is about the same as a distance between the first epitaxial source/drain and the second epitaxial source/drain.

Dummy Gate Cutting Process and Resulting Gate Structures (18354995)

Main Inventor

Shih-Yao Lin

Brief explanation

The patent application describes a method for forming gate isolation regions in a semiconductor device. Here are the key points:

• A dummy gate stack is formed and then etched to create an opening.
• A first dielectric layer is deposited into the opening.
• A second dielectric layer is deposited on top of the first dielectric layer and also extends into the opening.
• A planarization process is performed to create a gate isolation region using the first and second dielectric layers.
• The dummy gate stack is removed, resulting in trenches on both sides of the gate isolation region.
• Sidewall portions of the first dielectric layer are removed through a first etching process.
• The second dielectric layer is thinned through a second etching process.
• Replacement gates are formed in the trenches.

Overall, this method provides a way to create gate isolation regions and replacement gates in a semiconductor device.

Abstract

A method includes forming a dummy gate stack, etching the dummy gate stack to form an opening, depositing a first dielectric layer extending into the opening, and depositing a second dielectric layer on the first dielectric layer and extending into the opening. A planarization process is then performed to form a gate isolation region including the first dielectric layer and the second dielectric layer. The dummy gate stack is then removed to form trenches on opposing sides of the gate isolation region. The method further includes performing a first etching process to remove sidewall portions of the first dielectric layer, performing a second etching process to thin the second dielectric layer, and forming replacement gates in the trenches.

FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS (18343687)

Main Inventor

Miin-Jang CHEN

Brief explanation

The patent application describes a MFM (Metal-Film-Metal) structure that consists of a resistance component, an inductance component, and a capacitance component. 

• The MFM device functions as a series LC circuit with the resistance component connected in parallel with the capacitance component.
• The MFM structure can be utilized as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

Abstract

Techniques in accordance with embodiments described herein are directed to a MFM structure that includes a resistance component, an inductance component and a capacitance component. The MFM device is equivalent to a series LC circuit with the resistance component coupled in parallel with the capacitance component. The MFM structure is used as a series LC resonant circuit, band-pass circuit, band-stop circuit, low-pass filter, high-pass filter, oscillators, or negative capacitors.

METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS (18356080)

Main Inventor

Ka-Hing FUNG

Brief explanation

The patent application describes a method for forming gate spacers and an epitaxy source/drain structure in a semiconductor device.

• The method involves forming a gate stack over a fin of a substrate.
• Multiple dielectric layers are sequentially deposited over the gate stack, with the second dielectric layer having a lower dielectric constant than the first and third dielectric layers.
• A filling dielectric is also deposited over the gate stack.
• A dielectric cap is formed over the dielectric layers and the filling dielectric.
• The dielectric cap, dielectric layers, and filling dielectric are etched simultaneously to form gate spacers on the sidewalls of the gate stack and expose the top surface of the fin.
• After the gate spacers are formed, an epitaxy source/drain structure is formed in contact with one of the gate spacers and the top surface of the fin.

Abstract

A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

MULTI-PHASE VOLTAGE REGULATOR SYSTEM (18355590)

Main Inventor

Russell KINDER

Brief explanation

The patent application describes multiphase voltage regulator systems that use parallel signal pathways to maintain a constant voltage output.

• The parallel signal pathways charge and discharge energy storage elements to generate energy.
• The discharged energy is combined to create the analog output signal.
• One of the charging signals is compared to a reference input signal to determine the error between the reference and the output signal.
• The charging signals are adjusted based on this error to minimize the difference.
• Manufacturing variations and misalignment tolerances can cause mismatches between the parallel signal pathways.
• The remaining charging signals are compared to the global error correction signal to quantify these mismatches.
• The remaining charging signals are adjusted based on the local error correction signals to compensate for the mismatches.

Abstract

Multiphase voltage regulator systems are disclosed which include parallel signal pathways that functionally cooperate to provide an analog output signal at a constant, or substantially constant, voltage. The parallel signal pathways generate energy storage element charging signals to charge and/or discharge energy storage elements. Energy provided by discharging energy storage elements is thereafter combined to provide the analog output signal. Moreover, the parallel signal pathways compare one of the energy storage element charging signals with a reference input signal to provide a global error correction signal representing a difference, or error, between the reference input signal and the analog output signal. The parallel signal pathways thereafter adjust the energy storage element charging signals in accordance with the global error correction signal to lessen this difference or error. In some situations, manufacturing variations and/or misalignment tolerances present within the parallel signal pathways can cause mismatches between the parallel signal pathways. In these situations, the parallel signal pathways compare remaining energy storage element charging signals to the global error correction signal to provide local error correction signals to quantify these mismatches. Thereafter, the parallel signal pathways adjust the remaining energy storage element charging signals in accordance with the one or more local error correction signals to compensate for these mismatches.

Memory Device and Method for Forming Thereof (18347985)

Main Inventor

Chih-Chuan Yang

Brief explanation

The patent application describes a semiconductor device that includes a memory cell and a dummy region.

• The memory cell consists of a transistor.
• The dummy region contains a cut-off transistor.
• The first terminal of the cut-off transistor is connected to the second terminal of the memory cell transistor.
• The third terminal of the cut-off transistor is connected to ground.

The innovation in this patent application is:

• The inclusion of a dummy region adjacent to the memory cell in a semiconductor device.
• The use of a cut-off transistor in the dummy region.
• The electrical coupling of the first terminal of the cut-off transistor to the second terminal of the memory cell transistor.
• The electrical coupling of the third terminal of the cut-off transistor to ground.

Abstract

A semiconductor device includes a first memory cell and a dummy region adjacent to the first memory cell. The first memory cell includes a first transistor. The dummy region includes a cut-off transistor. The cut-off transistor has a first terminal electrically coupled to a second terminal of the first transistor. The cut-off transistor has a third terminal electrically coupled to ground.

PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM (18355889)

Main Inventor

Shih-Han Huang

Brief explanation

The abstract describes a static random access memory (SRAM) cell design with specific features and arrangements of gates and contacts.

• The SRAM cell includes two gates that extend in a certain direction, with a gap separating them.
• There is a Vcc contact that also extends in the same direction, but it does not overlap with the gap between the gates.
• A Vss contact, which is smaller than the Vcc contact, is also present and has a segment that is positioned to the gap between the gates.
• The Vss contact is separated from the first gate by another gap in a perpendicular direction.

In summary, this patent application describes a specific configuration of gates and contacts in an SRAM cell design.

Abstract

A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

CAPACITOR, MEMORY DEVICE, AND METHOD (18352738)

Main Inventor

Chung-Liang CHENG

Brief explanation

The patent application describes a device that includes a substrate, with two nanostructures placed on top of it. 

• The first nanostructure is made of a semiconductor material and has a higher resistance.
• The second nanostructure is made of a conductor material and has a lower resistance.

Both nanostructures are positioned at the same height above the substrate but are laterally offset from each other.

• The first nanostructure is surrounded by a first gate structure, while the second nanostructure is surrounded by a second gate structure.

Abstract

A device includes a substrate. A first nanostructure is over the substrate, and includes a semiconductor having a first resistance. A second nanostructure is over the substrate, is offset laterally from the first nanostructure, is at about the same height above the substrate as the first nanostructure, and includes a conductor having a second resistance lower than the first resistance. A first gate structure is over and wrapped around the first nanostructure, and a second gate structure is over and wrapped around the second nanostructure.

METHOD FOR MANUFACTURING MEMORY DEVICE (18353569)

Main Inventor

Ya-Jui TSOU

Brief explanation

The patent application describes a method for forming a memory stack on a substrate.

• The memory stack is covered with a dielectric layer.
• An opening is created in the dielectric layer, but it does not expose the memory stack.
• A spin-orbit-torque (SOT) layer is formed within the opening.
• A free layer is formed over the dielectric layer to connect the memory stack and the SOT layer.

Abstract

A method includes forming a memory stack over a substrate. A dielectric layer is deposited to cover the memory stack. An opening is formed in the dielectric layer. The opening does not expose the memory stack. A spin-orbit-torque (SOT) layer is formed in the opening. A free layer is formed over the dielectric layer to interconnect the memory stack and the SOT layer.