US Patent Application 18354801. Silicon Phosphide Semiconductor Device simplified abstract

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Silicon Phosphide Semiconductor Device

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.


Inventor(s)

Tzu-Ching Lin of Hsinchu (TW)

Tuoh Bin Ng of Hsinchu (TW)

Silicon Phosphide Semiconductor Device - A simplified explanation of the abstract

This abstract first appeared for US patent application 18354801 titled 'Silicon Phosphide Semiconductor Device

Simplified Explanation

The patent application describes a method for forming source/drain regions in a semiconductor device and a semiconductor device that includes these regions.

  • The method involves etching a semiconductor fin to create a recess, with the fin having sidewalls and a bottom surface.
  • A source/drain region is then formed in the recess using a single continuous material that extends from the bottom surface to above the top surface of the semiconductor fin.
  • The precursor gas used for forming the source/drain region includes phosphine (PH) and either arsine (AsH) or monomethylsilane (CHSi).
  • Finally, a gate is formed over the semiconductor fin adjacent to the source/drain region, with the gate extending perpendicular to the direction of the fin.


Original Abstract Submitted

A method for forming source/drain regions in a semiconductor device and a semiconductor device including source/drain regions formed by the method are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction; forming a source/drain region in the first recess, the source/drain region including a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region including phosphine (PH) and at least one of arsine (AsH) or monomethylsilane (CHSi); and forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.