US Patent Application 18352595. Semiconductor Device with Curved Conductive Lines and Method of Forming the Same simplified abstract
Semiconductor Device with Curved Conductive Lines and Method of Forming the Same
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Shu-Shen Yeh of Taoyuan City (TW)
Che-Chia Yang of Taipei City (TW)
Po-Yao Lin of Zhudong Township (TW)
Semiconductor Device with Curved Conductive Lines and Method of Forming the Same - A simplified explanation of the abstract
This abstract first appeared for US patent application 18352595 titled 'Semiconductor Device with Curved Conductive Lines and Method of Forming the Same
Simplified Explanation
The abstract describes a package structure for an integrated circuit die.
- The package structure includes a first integrated circuit die and a redistribution structure bonded to it.
- The redistribution structure has a first metallization pattern in a first dielectric layer, which includes multiple first conductive features.
- Each first conductive feature consists of a first conductive via in the first dielectric layer and a first conductive line over the first dielectric layer, connected to the respective first conductive via.
- The first conductive lines have a curved shape in a plan view.
- There is a second dielectric layer over the first dielectric layer and the first metallization pattern.
- The second dielectric layer contains a second metallization pattern, which includes multiple second conductive vias in the second dielectric layer.
- Each second conductive via is positioned above and electrically connected to a respective first conductive line.
Original Abstract Submitted
An embodiment is package structure including a first integrated circuit die, a redistribution structure bonded to the first integrated circuit die, the redistribution structure including a first metallization pattern in a first dielectric layer, the first metallization pattern including a plurality of first conductive features, each of the first conductive features including a first conductive via in the first dielectric layer and first conductive line over the first dielectric layer and electrically coupled to the respective first conductive via, each of the first conductive lines comprising a curve in a plan view, a second dielectric layer over the first dielectric layer and the first metallization pattern, and a second metallization pattern in the second dielectric layer, the second metallization pattern including a plurality of second conductive via in the second dielectric layer, each of the second conductive vias being over and electrically coupled to a respective first conductive line.
