Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on November 9th, 2023
Summary of the patent applications from Taiwan Semiconductor Manufacturing Co., Ltd. on November 9th, 2023
Taiwan Semiconductor Manufacturing Co., Ltd. has recently filed several patents related to semiconductor devices and memory technologies. These patents cover various aspects of memory stack formation, gate and contact configurations, voltage regulator systems, gate isolation regions, and gate spacers. Notable applications include the use of spin-orbit-torque layers in memory stacks, the inclusion of dummy regions in semiconductor devices, and the formation of gate isolation regions using dummy gate stacks. Here is a summary of the recent patents filed by Taiwan Semiconductor Manufacturing Co., Ltd.:
- Memory stack formation: A method for forming a memory stack on a substrate, including the use of a dielectric layer and a spin-orbit-torque layer. - Gate and contact configurations: A device with two nanostructures made of different materials and positioned at the same height but laterally offset from each other, surrounded by different gate structures. - SRAM cell design: A specific design of an SRAM cell with specific arrangements of gates and contacts, including Vcc and Vss contacts. - Dummy regions in semiconductor devices: The inclusion of a dummy region adjacent to a memory cell in a semiconductor device, containing a cut-off transistor connected to the memory cell transistor and ground. - Voltage regulator systems: Multiphase voltage regulator systems using parallel signal pathways to maintain a constant voltage output, with error correction and compensation for manufacturing variations and misalignments. - Gate isolation regions: A method for forming gate isolation regions in a semiconductor device using dummy gate stacks, dielectric layers, and planarization processes. - Gate spacers and epitaxy source/drain structure: A method for forming gate spacers and an epitaxy source/drain structure in a semiconductor device using multiple dielectric layers and etching processes. - MFM structure: A Metal-Film-Metal structure functioning as a series LC circuit with various applications such as resonant circuits, filters, and oscillators. - Gates with air gaps: Gates with air gaps between the gate electrode and gate dielectric on both sidewalls, covered by a dielectric cap, positioned between epitaxial source/drain regions. - Epitaxy structure in semiconductor devices: A semiconductor device with a semiconductor fin and an epitaxy structure in a recess of the fin, consisting of different portions with varying percentages of germanium atoms.
Notable applications:
- Memory stack formation with spin-orbit-torque layers.
- Inclusion of dummy regions in semiconductor devices.
- Gate isolation regions using dummy gate stacks.
- Gates with air gaps and dielectric caps.
- Epitaxy structures with varying germanium atom percentages.
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on November 9th, 2023
- 1.1 SLURRY ENHANCEMENT FOR POLISHING SYSTEM (18355884)
- 1.2 Self-Aligned Acoustic Hole Formation in Piezoelectrical MEMS Microphone (17811109)
- 1.3 Integrated 3DIC With Stacked Photonic Dies and Method Forming Same (18356831)
- 1.4 PHOTONIC DEVICE (18352727)
- 1.5 MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS (18222344)
- 1.6 MATERIALS AND METHODS FOR FORMING RESIST BOTTOM LAYER (18352556)
- 1.7 Integrated Circuit Overlay Test Patterns And Method Thereof (18357220)
- 1.8 OVERLAY MARKS FOR REDUCING EFFECT OF BOTTOM LAYER ASYMMETRY (18356710)
- 1.9 Fingerprint Sensor in InFO Structure and Formation Method (18348460)
- 1.10 MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18352872)
- 1.11 Method of Filling Gaps with Carbon and Nitrogen Doped Film (18351064)
- 1.12 Method of Manufacturing Semiconductor Devices (18356636)
- 1.13 Dipole-Engineered High-K Gate Dielectric and Method Forming Same (18356860)
- 1.14 REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGES (17890980)
- 1.15 Dielectric Gap-Filling Process for Semiconductor Device (18351985)
- 1.16 Silicon Phosphide Semiconductor Device (18354801)
- 1.17 WAFER PROCESSING METHOD (18356084)
- 1.18 Passivation Structure with Planar Top Surfaces (18355799)
- 1.19 Fan-Out Package with Controllable Standoff (18351809)
- 1.20 Semiconductor Device and Method of Manufacture (17819381)
- 1.21 Interconnect Structure and Method of Forming Thereof (18351957)
- 1.22 Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof (18357500)
- 1.23 Semiconductor Device with Curved Conductive Lines and Method of Forming the Same (18352595)
- 1.24 Layout Design Methodology For Stacked Devices (18224434)
- 1.25 BACKSIDE PN JUNCTION DIODE (18356802)
- 1.26 METHOD OF FORMING A DUMMY FIN BETWEEN FIRST AND SECOND SEMICONDUCTOR FINS (18354844)
- 1.27 ISOLATION STRUCTURE FOR PREVENTING UNINTENTIONAL MERGING OF EPITAXIALLY GROWN SOURCE/DRAIN (18355143)
- 1.28 SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW (18355211)
- 1.29 2D-Channel Transistor Structure with Source-Drain Engineering (18354820)
- 1.30 Semiconductor Device and Method of Forming the Same (18353498)
- 1.31 Gate Air Spacer for Fin-Like Field Effect Transistor (18355073)
- 1.32 Dummy Gate Cutting Process and Resulting Gate Structures (18354995)
- 1.33 FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS (18343687)
- 1.34 METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS (18356080)
- 1.35 MULTI-PHASE VOLTAGE REGULATOR SYSTEM (18355590)
- 1.36 Memory Device and Method for Forming Thereof (18347985)
- 1.37 PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM (18355889)
- 1.38 CAPACITOR, MEMORY DEVICE, AND METHOD (18352738)
- 1.39 METHOD FOR MANUFACTURING MEMORY DEVICE (18353569)
Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on November 9th, 2023
SLURRY ENHANCEMENT FOR POLISHING SYSTEM (18355884)
Main Inventor
Chun-Hung Liao
Self-Aligned Acoustic Hole Formation in Piezoelectrical MEMS Microphone (17811109)
Main Inventor
Ting-Jung Chen
Integrated 3DIC With Stacked Photonic Dies and Method Forming Same (18356831)
Main Inventor
Chen-Hua Yu
PHOTONIC DEVICE (18352727)
Main Inventor
Sui-Ying HSU
MULTIFUNCTIONAL COLLIMATOR FOR CONTACT IMAGE SENSORS (18222344)
Main Inventor
Hsin-Yu CHEN
MATERIALS AND METHODS FOR FORMING RESIST BOTTOM LAYER (18352556)
Main Inventor
Jing Hong Huang
Integrated Circuit Overlay Test Patterns And Method Thereof (18357220)
Main Inventor
Tseng Chin Lo
OVERLAY MARKS FOR REDUCING EFFECT OF BOTTOM LAYER ASYMMETRY (18356710)
Main Inventor
Hung-Chih Hsieh
Fingerprint Sensor in InFO Structure and Formation Method (18348460)
Main Inventor
Chih-Hua Chen
MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18352872)
Main Inventor
Zong-You LUO
Method of Filling Gaps with Carbon and Nitrogen Doped Film (18351064)
Main Inventor
Wan-Yi Kao
Method of Manufacturing Semiconductor Devices (18356636)
Main Inventor
Tzu-Ang Chao
Dipole-Engineered High-K Gate Dielectric and Method Forming Same (18356860)
Main Inventor
Te-Yang Lai
REVERSED TONE PATTERNING METHOD FOR DIPOLE INCORPORATION FOR MULTIPLE THRESHOLD VOLTAGES (17890980)
Main Inventor
Lung-Kun CHU
Dielectric Gap-Filling Process for Semiconductor Device (18351985)
Main Inventor
Cheng-I Lin
Silicon Phosphide Semiconductor Device (18354801)
Main Inventor
Tzu-Ching Lin
WAFER PROCESSING METHOD (18356084)
Main Inventor
Yan-Hong LIU
Passivation Structure with Planar Top Surfaces (18355799)
Main Inventor
Yi-Hsiu Chen
Fan-Out Package with Controllable Standoff (18351809)
Main Inventor
Po-Hao Tsai
Semiconductor Device and Method of Manufacture (17819381)
Main Inventor
Chin-Yi Lin
Interconnect Structure and Method of Forming Thereof (18351957)
Main Inventor
Shu-Cheng Chin
Partial Barrier Free Vias for Cobalt-Based Interconnects and Methods of Fabrication Thereof (18357500)
Main Inventor
Tsung-Ling Tsai
Semiconductor Device with Curved Conductive Lines and Method of Forming the Same (18352595)
Main Inventor
Chia-Kuei Hsu
Layout Design Methodology For Stacked Devices (18224434)
Main Inventor
Fong-Yuan CHANG
BACKSIDE PN JUNCTION DIODE (18356802)
Main Inventor
Yu-Xuan Huang
METHOD OF FORMING A DUMMY FIN BETWEEN FIRST AND SECOND SEMICONDUCTOR FINS (18354844)
Main Inventor
Shih-Yao Lin
ISOLATION STRUCTURE FOR PREVENTING UNINTENTIONAL MERGING OF EPITAXIALLY GROWN SOURCE/DRAIN (18355143)
Main Inventor
Ta-Chun Lin
SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW (18355211)
Main Inventor
Mrunal A. Khaderbad
2D-Channel Transistor Structure with Source-Drain Engineering (18354820)
Main Inventor
Dhanyakumar Mahaveer Sathaiya
Semiconductor Device and Method of Forming the Same (18353498)
Main Inventor
Chia-Ming Chang
Gate Air Spacer for Fin-Like Field Effect Transistor (18355073)
Main Inventor
Chien-Ning Yao
Dummy Gate Cutting Process and Resulting Gate Structures (18354995)
Main Inventor
Shih-Yao Lin
FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS (18343687)
Main Inventor
Miin-Jang CHEN
METHOD OF FORMING FINFET WITH LOW-DIELECTRIC-CONSTANT GATE ELECTRODE SPACERS (18356080)
Main Inventor
Ka-Hing FUNG
MULTI-PHASE VOLTAGE REGULATOR SYSTEM (18355590)
Main Inventor
Russell KINDER
Memory Device and Method for Forming Thereof (18347985)
Main Inventor
Chih-Chuan Yang
PREVENTING GATE-TO-CONTACT BRIDGING BY REDUCING CONTACT DIMENSIONS IN FINFET SRAM (18355889)
Main Inventor
Shih-Han Huang
CAPACITOR, MEMORY DEVICE, AND METHOD (18352738)
Main Inventor
Chung-Liang CHENG
METHOD FOR MANUFACTURING MEMORY DEVICE (18353569)
Main Inventor
Ya-Jui TSOU
