US Patent Application 18355211. SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW simplified abstract

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SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.


Inventor(s)

Mrunal A. Khaderbad of Hsinchu City (TW)

Pang-Yen Tsai of Jhubei City (TW)

Yasutoshi Okuno of Hsinchu (TW)

SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW - A simplified explanation of the abstract

This abstract first appeared for US patent application 18355211 titled 'SELECTIVE DUAL SILICIDE FORMATION USING A MASKLESS FABRICATION PROCESS FLOW

Simplified Explanation

The patent application describes a method for selectively forming dielectric and silicide layers on different types of transistors in a semiconductor device.

  • The method involves forming a first dielectric layer over the source/drain region of a first type of transistor, but not over the source/drain region of a second type of transistor.
  • The first type of transistor and the second type of transistor have different types of conductivity.
  • A first silicide layer is then selectively formed over the source/drain region of the second type of transistor, but not over the source/drain region of the first type of transistor.
  • The first dielectric layer is removed.
  • Finally, a second silicide layer is formed over the source/drain region of the first type of transistor.


Original Abstract Submitted

A first dielectric layer is selectively formed such that the first dielectric layer is formed over a source/drain region of a first type of transistor but not over a source/drain region of a second type of transistor. The first type of transistor and the second type of transistor have different types of conductivity. A first silicide layer is selectively formed such that the first silicide layer is formed over the source/drain region of the second type of transistor but not over the source/drain region of the first type of transistor. The first dielectric layer is removed. A second silicide layer is formed over the source/drain region of the first type of transistor.

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