US Patent Application 18357220. Integrated Circuit Overlay Test Patterns And Method Thereof simplified abstract
Contents
Integrated Circuit Overlay Test Patterns And Method Thereof
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Tseng Chin Lo of Hsinchu City (TW)
Ying-Jung Chen of Hsinchu (TW)
Kung-Cheng Lin of Hsinchu (TW)
Meng Lin Chang of Hsinchu (TW)
Integrated Circuit Overlay Test Patterns And Method Thereof - A simplified explanation of the abstract
This abstract first appeared for US patent application 18357220 titled 'Integrated Circuit Overlay Test Patterns And Method Thereof
Simplified Explanation
- The patent application is about integrated circuits and methods for measuring overlap. - The integrated circuit described in the patent includes multiple functional cells and at least one gap next to a functional cell. - Within the gap, there is a test pattern cell called the first overlay test pattern cell. - The first overlay test pattern cell contains a certain number of patterns arranged in a specific direction at a specific pitch. - The pitch of the patterns is smaller than the smallest wavelength of visible light. - The purpose of this invention is to provide a method for measuring overlap in integrated circuits using the first overlay test pattern cell.
Original Abstract Submitted
Integrated circuits and methods for overlap measure are provided. In an embodiment, an integrated circuit includes a plurality of functional cells including at least one gap disposed adjacent to at least one functional cell of the plurality of functional cells and a first overlay test pattern cell disposed within the at least one gap, wherein the first overlay test pattern cell includes a first number of patterns disposed along a first direction at a first pitch. The first pitch is smaller than a smallest wavelength on a full spectrum of humanly visible lights.
