Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on November 2nd, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Co., Ltd. on November 2nd, 2023

Taiwan Semiconductor Manufacturing Co., Ltd. has recently filed several patents related to semiconductor devices and manufacturing processes. These patents cover various aspects of memory structures, interconnect structures, FinFET devices, source/drain regions, semiconductor channel layers, gate structures, and integrated circuits. Notable applications include:

• A method for creating a monitor cell that is identical to the flash memory cells in an embedded memory array. The monitor cell is made at the same time as the memory array cells and includes a silicide protection layer to prevent contamination during manufacturing processes.
• A memory structure with a memory cell array and various components such as n-type wells, a pick-up region, and a second n-type well in the peripheral region.
• An interconnect structure with a dielectric block, conductive plugs, a substrate, and conductive lines. The conductive lines are connected to the conductive plugs and surrounded by the dielectric block and substrate.
• A FinFET device with a substrate, isolation structure, fin structure, and epitaxial structure. The epitaxial structure has a pentagon-like shape, and the interface between the epitaxial structure and the fin structure is lower than the top surface of the isolation structure.
• A method for forming a source/drain region in a semiconductor device by etching a semiconductor fin and epitaxially growing three layers of silicon germanium (SiGe) on the sidewalls of the recess.
• Semiconductor structures with hybrid fins made of silicon oxycarbonitride and silicon carbonitride, and a method of forming them.
• A semiconductor structure with multiple semiconductor channel layers, gate structures, and source/drain features stacked on top of each other. One of the semiconductor channel layers does not have any contact with the first source/drain feature.
• A method for forming a semiconductor device by depositing a dummy dielectric layer, dummy gate seed layer, and dummy gate material to create a precise dummy gate structure.
• An integrated circuit with a sidewall spacer formed using a low-k dielectric material, and a method for forming such a circuit. The spacer layer is positioned between the source/drain contact and the gate stack.
• A device with a substrate, semiconductor channel, and gate structure. The gate structure includes multiple layers such as a dielectric layer, metal layer with a specific work function, protection layers, and metal fill layer.

Overall, these patents demonstrate Taiwan Semiconductor Manufacturing Co., Ltd.'s focus on developing innovative semiconductor devices and manufacturing processes to improve performance and integration in the industry.

Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on November 2nd, 2023

Fabrication of a Polishing Pad for Chemical Mechanical Polishing (18349491)

Main Inventor

An-Hsuan Lee

AIR CURTAIN DEVICE AND WORKPIECE PROCESSING TOOL (17733657)

Main Inventor

Chia-Wei WU

Optical Transceiver and Manufacturing Method Thereof (18347188)

Main Inventor

Chen-Hua Yu

CROSSLINKABLE PHOTORESIST FOR EXTREME ULTRAVIOLET LITHOGRAPHY (17734981)

Main Inventor

Li-Po YANG

POLYMER CROSSLINK DE-CROSSLINK PROCESSES FOR RESIST PATTERNING (17734975)

Main Inventor

Yu-Chung SU

AUTOMATIC OPTICAL INSPECTION SYSTEM AND METHOD (17730585)

Main Inventor

I-Hsuan Chen

Post-CMP Cleaning and Apparatus (18349476)

Main Inventor

Fu-Ming Huang

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18351149)

Main Inventor

Zheng-Long CHEN

Structure and Method for Enhancing Robustness of ESD Device (18346589)

Main Inventor

Alexander Kalnitsky

Semiconductor Device and Method (18344441)

Main Inventor

Ching-Feng Fu

METAL GATE STRUCTURE CUTTING PROCESS (18345188)

Main Inventor

I-Wen Wu

DEPOSITION SYSTEM AND METHOD (18341506)

Main Inventor

Wen-Hao CHENG

HEAT DISSIPATION STRUCTURES (18347013)

Main Inventor

Po-Hsiang HUANG

SEMICONDUCTOR PACKAGE AND METHOD (17661622)

Main Inventor

Chen-Hua Yu

INTERCONNECT STRUCTURE PATTERN (17819678)

Main Inventor

Fu-Chiang KUO

Multi-Level Stacking of Wafers and Chips (18338107)

Main Inventor

Ming-Fa Chen

Integrated Circuit Package and Method Forming Same (18346319)

Main Inventor

Shin-Puu Jeng

INPUT/OUTPUT DEVICES (18349486)

Main Inventor

Sung-Hsin Yang

FinFET Devices with Dummy Fins Having Multiple Dielectric Layers (18338609)

Main Inventor

Jhon Jhy Liaw

Doping for Semiconductor Device with Conductive Feature (18350838)

Main Inventor

Su-Hao Liu

Hybrid Channel Semiconductor Device and Method (18352133)

Main Inventor

Pei-Yu Wang

Separate Epitaxy Layers for Nanowire Stack GAA Device (18220397)

Main Inventor

Tung Ying Lee

GATE STRUCTURE AND METHOD (18347480)

Main Inventor

Chung-Liang CHENG

INTEGRATED CIRCUIT WITH SIDEWALL SPACERS FOR GATE STACKS (18349448)

Main Inventor

Yen-Ting Chen

Semiconductor Device and Method (18342146)

Main Inventor

De-Wei Yu

SEMICONDUCTOR DEVICE WITH VARYING NUMBERS OF CHANNEL LAYERS AND METHOD OF FABRICATION THEREOF (18349617)

Main Inventor

Cheng-Ting Chung

POST-FORMATION MENDS OF DIELECTRIC FEATURES (18346020)

Main Inventor

Wan-Yi Kao

SOURCE/DRAIN REGIONS OF FINFET DEVICES AND METHODS OF FORMING SAME (18346511)

Main Inventor

Kun-Mu Li

Fin Field Effect Transistor (FinFET) Device and Method for Forming the Same (18338759)

Main Inventor

Zhe-Hao Zhang

INTERCONNECT STRUCTURE HAVING CONDUCTOR EXTENDING ALONG DIELECTRIC BLOCK (18344652)

Main Inventor

Jiun-Yi WU

Shared Pick-Up Regions for Memory Devices (17731781)

Main Inventor

Chih-Chuan Yang

STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY (18346056)

Main Inventor

Meng-Han LIN