US Patent Application 18352133. Hybrid Channel Semiconductor Device and Method simplified abstract

Hybrid Channel Semiconductor Device and Method

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Pei-Yu Wang of Hsinchu (TW)

Pei-Hsun Wang of Kaohsiung (TW)

Hybrid Channel Semiconductor Device and Method - A simplified explanation of the abstract

This abstract first appeared for US patent application 18352133 titled 'Hybrid Channel Semiconductor Device and Method

Simplified Explanation

The patent application describes a device with two semiconductor strips protruding from a substrate and surrounded by isolation material.

• The device includes a nanosheet structure over one of the semiconductor strips, separated by a first gate structure.
• The nanosheet structure is partially surrounded by the first gate structure.
• There is a first semiconductor channel region and a second semiconductor channel region over the other semiconductor strip.
• The first and second semiconductor channel regions are separated by a second gate structure.
• The second gate structure extends on the top surface of the second semiconductor strip.

Original Abstract Submitted

A device includes a first semiconductor strip protruding from a substrate, a second semiconductor strip protruding from the substrate, an isolation material surrounding the first semiconductor strip and the second semiconductor strip, a nanosheet structure over the first semiconductor strip, wherein the nanosheet structure is separated from the first semiconductor strip by a first gate structure including a gate electrode material, wherein the first gate structure partially surrounds the nanosheet structure, and a first semiconductor channel region and a semiconductor second channel region over the second semiconductor strip, wherein the first semiconductor channel region is separated from the second semiconductor channel region by a second gate structure including the gate electrode material, wherein the second gate structure extends on a top surface of the second semiconductor strip.