US Patent Application 17819678. INTERCONNECT STRUCTURE PATTERN simplified abstract

INTERCONNECT STRUCTURE PATTERN

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Fu-Chiang Kuo of Hsinchu City (TW)

Guan Yu Chen of New Taipei City (TW)

Hsin-Liang Chen of Hsinchu City (TW)

INTERCONNECT STRUCTURE PATTERN - A simplified explanation of the abstract

This abstract first appeared for US patent application 17819678 titled 'INTERCONNECT STRUCTURE PATTERN

Simplified Explanation

The patent application describes a structure consisting of a substrate, a circuit element, and two metallization layers. The circuit element is formed on the substrate. The first metallization layer is placed over the substrate and includes a metal line connected to the circuit element, as well as dummy metal lines extending in one direction. The second metallization layer is directly above the first metallization layer and includes a metal line connected to the first metal line, as well as dummy metal lines extending in a perpendicular direction. The purpose of this structure is to provide electrical connections between the circuit element and the metal lines in a compact and efficient manner.

• The patent application describes a structure for connecting a circuit element to metal lines on a substrate.
• The structure includes two metallization layers, with the first layer having a metal line connected to the circuit element and dummy metal lines extending in one direction.
• The second metallization layer is directly above the first layer and includes a metal line connected to the first metal line and dummy metal lines extending in a perpendicular direction.
• This structure allows for efficient and compact electrical connections between the circuit element and the metal lines.
• The invention aims to improve the performance and functionality of electronic devices by providing a more efficient and reliable structure for electrical connections.

Original Abstract Submitted

The present disclosure describes a structure with a substrate, a circuit element, a first metallization layer, and a second metallization layer. The circuit element is formed on the substrate. The first metallization layer is disposed over the substrate and includes a first metal line electrically connected to the circuit element and first dummy metal lines extending along a first direction. The second metallization layer is disposed directly above the first metallization layer and includes a second metal line electrically connected to the first metal line and second dummy metal lines extending along a second direction. The second direction is perpendicular to the first direction.