US Patent Application 18345188. METAL GATE STRUCTURE CUTTING PROCESS simplified abstract

METAL GATE STRUCTURE CUTTING PROCESS

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

I-Wen Wu of Hsinchu City (TW)

Chen-Ming Lee of Taoyuan County (TW)

Fu-Kai Yang of Hsinchu City (TW)

Mei-Yun Wang of Hsin-Chu (TW)

Chang-Yun Chang of Taipei (TW)

Ching-Feng Fu of Taichung City (TW)

Peng Wang of Hsinchu (TW)

METAL GATE STRUCTURE CUTTING PROCESS - A simplified explanation of the abstract

This abstract first appeared for US patent application 18345188 titled 'METAL GATE STRUCTURE CUTTING PROCESS

Simplified Explanation

The patent application describes a method for fabricating a semiconductor device with a fin structure and a gate structure. Here are the key points:

• The method begins by forming a fin that protrudes from a substrate.
• A gate structure is then formed across the fin.
• An epitaxial feature is formed over the fin.
• A dielectric layer is deposited to cover the epitaxial feature and the sidewalls of the gate structure.
• An etching process is performed to create a trench, which divides the gate structure into two segments and extends into the dielectric layer.
• A dielectric feature is formed within the trench.
• A portion of the dielectric feature located in a specific region is recessed.
• The dielectric layer is selectively etched to expose the epitaxial feature.
• Finally, a conductive feature is deposited in direct contact with the epitaxial feature and above the recessed portion of the dielectric feature.

Original Abstract Submitted

A method includes forming a fin protruding from a substrate, forming a gate structure across the fin, forming an epitaxial feature over the fin, depositing a dielectric layer covering the epitaxial feature and over sidewalls of the gate structure, performing an etching process to form a trench, the trench dividing the gate structure into first and second gate segments and extending into a region of the dielectric layer, forming a dielectric feature in the trench, recessing a portion of the dielectric feature located in the region, selectively etching the dielectric layer to expose the epitaxial feature, and depositing a conductive feature in physical contact with the epitaxial feature and directly above the portion of the dielectric feature.