US Patent Application 18338609. FinFET Devices with Dummy Fins Having Multiple Dielectric Layers simplified abstract

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FinFET Devices with Dummy Fins Having Multiple Dielectric Layers

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Jhon Jhy Liaw of Hsinchu County (TW)

FinFET Devices with Dummy Fins Having Multiple Dielectric Layers - A simplified explanation of the abstract

This abstract first appeared for US patent application 18338609 titled 'FinFET Devices with Dummy Fins Having Multiple Dielectric Layers

Simplified Explanation

The patent application describes a semiconductor device that includes a substrate and semiconductor fins oriented in one direction. It also includes multi-dielectric-layer (MDL) fins that are intermixed with the semiconductor fins and have different dielectric materials. The device further includes gate structures that are perpendicular to the semiconductor fins and are separated by the MDL fins.

  • Semiconductor device with substrate and semiconductor fins oriented in one direction
  • Includes multi-dielectric-layer (MDL) fins intermixed with the semiconductor fins
  • MDL fins have different dielectric materials in outer and inner layers
  • Gate structures are perpendicular to the semiconductor fins and spaced apart along the MDL fins
  • Gate structures engage both the semiconductor fins and the MDL fins


Original Abstract Submitted

A semiconductor device includes a substrate; semiconductor fins over the substrate and oriented lengthwise along a first direction; first multi-dielectric-layer (MDL) fins and second MDL fins over the substrate and oriented lengthwise along the first direction, wherein the first and the second MDL fins are intermixed with the semiconductor fins, wherein each of the first MDL fins and the second MDL fins includes an outer dielectric layer and an inner dielectric layer, wherein the outer dielectric layer and the inner dielectric layer have different dielectric materials; and gate structures oriented lengthwise along a second direction generally perpendicular to the first direction, wherein the gate structures are spaced from each other along the first direction, and are separated by the first MDL fins along the second direction, wherein the gate structures engage the semiconductor fins and the second MDL fins.

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