US Patent Application 18346056. STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY simplified abstract
STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY - A simplified explanation of the abstract
This abstract first appeared for US patent application 18346056 titled 'STRUCTURE AND METHOD FOR PREVENTING SILICIDE CONTAMINATION DURING THE MANUFACTURE OF MICRO-PROCESSORS WITH EMBEDDED FLASH MEMORY
Simplified Explanation
The patent application describes a method for creating a monitor cell that is identical to the flash memory cells in an embedded memory array.
- The monitor cell is made at the same time as the memory array cells, making it directly comparable in critical aspects.
- An aperture is created that goes through the control gate and dielectric to reach the floating gate of the monitor cell.
- To prevent contamination during a CMP process, a silicide protection layer (SPL) is formed over the exposed parts of the control gate before the silicide contact is formed on the floating gate.
- The SPL is created simultaneously with existing manufacturing processes to avoid additional steps.
Original Abstract Submitted
A method is provided in which a monitor cell is made that is substantially identical to the flash memory cells of an embedded memory array. The monitor cell is formed simultaneously with the cells of the memory array, and so in certain critical aspects, is exactly comparable. An aperture is formed that extends through the control gate and intervening dielectric to the floating gate of the monitor cell. To prevent silicide contamination during a subsequent CMP process, a silicide protection layer (SPL), such as a resist protective oxide, is formed over exposed portions of the control gate prior to formation of a silicide contact formed on the floating gate. The SPL is formed simultaneously with existing manufacturing processes to avoid additional process steps.
