US Patent Application 18338107. Multi-Level Stacking of Wafers and Chips simplified abstract

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Multi-Level Stacking of Wafers and Chips

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Ming-Fa Chen of Taichung City (TW)

Cheng-Feng Chen of Zhubei City (TW)

Sung-Feng Yeh of Taipei City (TW)

Chuan-An Cheng of Zhubei City (TW)

Multi-Level Stacking of Wafers and Chips - A simplified explanation of the abstract

This abstract first appeared for US patent application 18338107 titled 'Multi-Level Stacking of Wafers and Chips

Simplified Explanation

The patent application describes a method for bonding a wafer to a carrier and then bonding multiple chips over the wafer with gaps in between. The method includes a gap-filling process to fill the gaps, bonding a second carrier onto the chips and gap-filling regions, and removing the first carrier from the wafer. Electrical connectors are then formed to connect the chips through through-vias in the wafer.

  • Method for bonding a wafer to a carrier and bonding multiple chips over the wafer
  • Gaps are present between the chips
  • Gap-filling process is performed to fill the gaps with gap-filling regions
  • Second carrier is bonded onto the chips and gap-filling regions
  • First carrier is removed from the wafer
  • Electrical connectors are formed to connect the chips through through-vias in the wafer


Original Abstract Submitted

In a method, a wafer is bonded to a first carrier. The wafer includes a semiconductor substrate, and a first plurality of through-vias extending into the semiconductor substrate. The method further includes bonding a plurality of chips over the wafer, with gaps located between the plurality of chips, performing a gap-filling process to form gap-filling regions in the gaps, bonding a second carrier onto the plurality of chips and the gap-filling regions, de-bonding the first carrier from the wafer, and forming electrical connectors electrically connecting to conductive features in the wafer. The electrical connectors are electrically connected to the plurality of chips through the first plurality of through-vias.

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