Taiwan Semiconductor Manufacturing Co., Ltd. patent applications published on October 12th, 2023

Summary of the patent applications from Taiwan Semiconductor Manufacturing Co., Ltd. on October 12th, 2023

Taiwan Semiconductor Manufacturing Co., Ltd. has recently filed several patents related to memory devices, semiconductor devices, reducing inter-symbol interference in communication channels, multi-gate devices, semiconductor structures, and metal gate structures with sidewall spacers. These patents demonstrate the company's focus on developing innovative technologies in the semiconductor industry.

Notable applications of these patents include:

• Memory devices with improved component arrangement and material composition.
• Semiconductor devices with multiple active regions and gates for enhanced performance.
• Apparatus and methods for reducing inter-symbol interference in communication channels.
• Fabrication methods for multi-gate devices with nanosheets.
• Semiconductor structures with air gaps for improved performance and efficiency.
• Semiconductor structures with unique fin and gate configurations.
• Semiconductor devices with doped semiconductor layers matching the shape of the semiconductor fin.
• Metal gate structures with recessed top surfaces and wider metal cap layers.
• Devices with specific arrangements of layers and structures for optimal performance.

Overall, these patents demonstrate Taiwan Semiconductor Manufacturing Co., Ltd.'s commitment to advancing semiconductor technology and developing innovative solutions for various applications in the industry.

Patent applications for Taiwan Semiconductor Manufacturing Co., Ltd. on October 12th, 2023

Chemical Mechanical Planarization Tool (18334526)

Main Inventor

Tung-Kai Chen

EXTREME ULTRAVIOLET LITHOGRAPHY METHOD, EXTREME ULTRAVIOLET MASK AND FORMATION METHOD THEREOF (18334640)

Main Inventor

Chih-Tsung SHIH

Brief explanation

The abstract describes a method for creating an extreme ultraviolet (EUV) mask. This involves creating a stack of alternating layers of molybdenum (Mo) and silicon (Si) on a mask substrate. A layer of ruthenium is then added on top of the stack, which is doped with certain elements. An absorber layer is formed over the ruthenium layer, and then the absorber layer is etched to create a pattern.

Abstract

A method of forming an extreme ultraviolet (EUV) mask includes forming a multilayer Mo/Si stack comprising alternating stacked Mo and Si layers over a mask substrate; forming a ruthenium capping layer over the multilayer Mo/Si stack; doping the ruthenium capping layer with a halogen element, a pentavalent element, a hexavalent element or combinations thereof; forming an absorber layer over the ruthenium capping layer; and etching the absorber layer to form a pattern in the absorber layer.

Metal-Compound-Removing Solvent And Method In Lithography (18336399)

Main Inventor

An-Ren Zi

Brief explanation

In this study, a process called extreme ultraviolet (EUV) lithography was used to create a pattern on a wafer coated with a photoresist layer containing a metal-containing material. After the lithography process, the wafer was cleaned using a specific cleaning fluid. This cleaning fluid contained a solvent with specific solubility parameters, including a range of values for delta D, delta P, and delta H. Additionally, the solvent contained either an acid with a low acid dissociation constant or a base with a high acid dissociation constant. The purpose of the cleaning process was to remove the metal-containing material from the wafer.

Abstract

A photoresist layer is coated over a wafer. The photoresist layer includes a metal-containing material. An extreme ultraviolet (EUV) lithography process is performed to the photoresist layer to form a patterned photoresist. The wafer is cleaned with a cleaning fluid to remove the metal-containing material. The cleaning fluid includes a solvent having Hansen solubility parameters of delta D in a range between 13 and 25, delta P in a range between 3 and 25, and delta H in a range between 4 and 30. The solvent contains an acid with an acid dissociation constant less than 4 or a base with an acid dissociation constant greater than 9.

Geometric Mask Rule Check With Favorable and Unfavorable Zones (18334551)

Main Inventor

Shih-Ming Chang

Brief explanation

The abstract describes a method that involves creating a map based on diffraction patterns, dividing it into favorable and unfavorable zones. Sub-resolution patterns are then placed in the favorable zone and undergo geometric operations to generate modified patterns. These modified patterns extend into the favorable zone and are positioned away from the unfavorable zone.

Abstract

A method includes generating a diffraction map from a plurality of target patterns, generating a favorable zone and an unfavorable zone from the diffraction map, placing a plurality of sub-resolution patterns in the favorable zone, and performing a plurality of geometric operations on the plurality of sub-resolution patterns to generate modified sub-resolution patterns. The modified sub-resolution patterns extend into the favorable zone, and are away from the unfavorable zone.

CURRENT STEERING IN READING MAGNETIC TUNNEL JUNCTION (18332674)

Main Inventor

Gaurav GUPTA

Brief explanation

The abstract describes a type of read circuit for a magnetic tunnel junction (MTJ) device. The circuit includes a current steering element that is connected to the read path. The current steering element maintains a larger current at one node to ensure reliable voltage or current sensing. At the other node, a smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node, allowing the current at the first node to be used to infer the current at the second node, which is affected by the resistance value of the MTJ.

Abstract

The disclosed MTJ read circuits include a current steering element coupled to the read path. At a first node of the current steering element, a proportionally larger current is maintained to meet the requirements of a reliable voltage or current sensing. At a second node of the current steering element, a proportionally smaller current is maintained, which passes through the MTJ structure. The current at the first node is proportional to the current at the second node such that sensing the current at the first node infers the current at the second node, which is affected by the MTJ resistance value.

SOT-MRAM WITH SHARED SELECTOR (18321196)

Main Inventor

MingYuan Song

Brief explanation

The abstract describes a magnetic memory device that consists of several components. These include a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring placed over the MTJ stack, a first terminal connected to one end of the SOT induction wiring, a second terminal connected to the other end of the SOT induction wiring, and a shared selector layer connected to the first terminal.

Abstract

A magnetic memory device includes a magnetic tunnel junction (MTJ) stack, a spin-orbit torque (SOT) induction wiring disposed over the MTJ stack, a first terminal coupled to a first end of the SOT induction wiring, a second terminal coupled to a second end of the SOT induction wiring, and a shared selector layer coupled to the first terminal.

CHEMICAL MECHANICAL POLISHING CLEANING SYSTEM WITH TEMPERATURE CONTROL FOR DEFECT REDUCTION (18334181)

Main Inventor

Ssutzu CHEN

Brief explanation

The abstract describes a cleaning system that is used after a chemical mechanical polishing (CMP) process to remove contaminants from a substrate. The system includes a cleaning module that receives the substrate and uses a cleaning solution to remove the contaminants. There is also a cleaning solution supply system that provides the cleaning solution to the cleaning module. This supply system includes a temperature control system, which consists of a heating device to heat the cleaning solution, a cooling device to cool the cleaning solution, a temperature sensor to monitor the temperature of the cleaning solution, and a temperature controller to control the heating and cooling devices.

Abstract

A cleaning system includes at least one cleaning module configured to receive a substrate after a chemical mechanical polishing (CMP) process and to remove contaminants on the substrate using a cleaning solution. The cleaning system further includes a cleaning solution supply system configured to supply the cleaning solution to the at least one cleaning module. The cleaning solution supply system includes at least one temperature control system. The at least one temperature control system includes a heating device configured to heat the cleaning solution, a cooling device configured to cool the cleaning solution, a temperature sensor configured to monitor a temperature of the cleaning solution, and a temperature controller configured to control the heating device and the cooling device.

Low-k Feature Formation Processes and Structures Formed Thereby (18326370)

Main Inventor

Wan-Yi Kao

Brief explanation

The abstract describes semiconductor device structures with low-k features, which refers to features that have a low dielectric constant. The abstract mentions different examples of low-k features, such as a surface modification layer, gate spacers, and a contact etch stop layer. These features are designed to protect low-k features during processing. The abstract also mentions that methods for forming these low-k features are described. Overall, the abstract provides a brief overview of the topic without overselling any specific claims or providing a title.

Abstract

Semiconductor device structures having low-k features and methods of forming low-k features are described herein. Some examples relate to a surface modification layer, which may protect a low-k feature during subsequent processing. Some examples relate to gate spacers that include a low-k feature. Some examples relate to a low-k contact etch stop layer. Example methods are described for forming such

METHOD OF SUPPLYING CHEMICAL LIQUID (18332261)

Main Inventor

Yu-Cheng CHANG

Brief explanation

This abstract describes a method for supplying a chemical liquid to a processing tool. The method involves placing a drum containing the chemical liquid into a chamber of a chemical liquid supplying system. The drum is connected to a testing pipe, and the chemical liquid is pumped from the drum into the testing pipe. The condition of the chemical liquid flowing through the testing pipe is continuously monitored. Based on this condition, it is determined whether the chemical liquid should be supplied to the processing tool or not.

Abstract

A method includes moving a drum containing a chemical liquid into a chamber of a chemical liquid supplying system. The drum is connected with a testing pipe. The chemical liquid is pumped from the drum to the testing pipe. A condition of the chemical liquid flowing through the testing pipe is monitored. Whether the chemical liquid is supplied to a processing tool is determined based on the condition of the chemical liquid.

MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE (18336137)

Main Inventor

Yu-Hung Cheng

Brief explanation

The abstract describes a new type of deep trench isolation structure for high voltage semiconductor-on-insulator devices. This structure surrounds the active region of a semiconductor-on-insulator substrate and consists of two insulator sidewall spacers with a multilayer silicon-comprising isolation structure in between. The multilayer structure includes a top polysilicon portion and a bottom silicon portion, with the bottom portion being doped with boron. The bottom polysilicon portion is formed through a selective deposition process, while the top polysilicon portion is formed through a non-selective deposition process.

Abstract

Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.

INTERFACE TRAP CHARGE DENSITY REDUCTION (18329396)

Main Inventor

Szu-Chi Yang

Brief explanation

The abstract describes a method for manufacturing a semiconductor device. The method involves creating two fins on a substrate using different semiconductor materials, then applying a semiconductor cap layer over the fins. Finally, the cap layer is heated at a specific temperature while some parts of it are exposed.

Abstract

The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.

SEMICONDUCTOR DEVICE AND METHOD (18335806)

Main Inventor

Shih-Chieh Wu

Brief explanation

The abstract describes a method for manufacturing a semiconductor device. It involves creating two fins on a substrate, with a metal gate stack formed over them. A layer of dielectric material is deposited over the gate stack, and a gate contact is created to physically connect with the metal gate stack. The gate contact is positioned between the two fins and is closer to one of the fins if the distance between the fins is larger than a certain threshold.

Abstract

In an embodiment, a method includes: forming a first fin extending from a substrate; forming a second fin extending from the substrate, the second fin being spaced apart from the first fin by a first distance; forming a metal gate stack over the first fin and the second fin; depositing a first inter-layer dielectric over the metal gate stack; and forming a gate contact extending through the first inter-layer dielectric to physically contact the metal gate stack, the gate contact being laterally disposed between the first fin and the second fin, the gate contact being spaced apart from the first fin by a second distance, where the second distance is less than a second predetermined threshold when the first distance is greater than or equal to a first predetermined threshold.

SOURCE/DRAIN EPITAXIAL STRUCTURES FOR SEMICONDUCTOR DEVICES (18336370)

Main Inventor

Shahaji B. MORE

Brief explanation

The abstract describes a method for creating a semiconductor device with optimized dimensions. The method involves creating two fin structures on a substrate and adding a spacer layer on top. A first spacer structure is formed next to the first fin structure, and a first epitaxial structure is formed next to the first spacer structure. The first and second fin structures are separated by an isolation layer. A second spacer structure is then formed next to the second fin structure, and a second epitaxial structure is formed next to the second spacer structure. The second spacer structure is taller than the first spacer structure. The second epitaxial structure contains a different type of dopant compared to the first epitaxial structure.

Abstract

The present disclosure describes a method of forming a semiconductor device having epitaxial structures with optimized dimensions. The method includes forming first and second fin structures on a substrate, forming a spacer layer on the first and second fin structures, forming a first spacer structure adjacent to the first fin structure, and forming a first epitaxial structure adjacent to the first spacer structure. The first and second fin structures are separated by an isolation layer. The first spacer structure has a first height above the isolation layer. The method further includes forming a second spacer structure adjacent to the second fin structure and forming a second epitaxial structure adjacent to the second spacer structure. The second spacer structure has a second height above the isolation layer greater than the first height. The second epitaxial structure includes a type of dopant different from the first epitaxial structure.

METHODS OF FORMING CONTACT FEATURES IN FIELD-EFFECT TRANSISTORS (18336168)

Main Inventor

Yi-Hsiung Lin

Brief explanation

This abstract describes a semiconductor structure that consists of two semiconductor fins placed next to each other on a substrate. A metal gate structure is positioned over these fins in a direction perpendicular to their length. On top of each fin, there is an epitaxial source/drain (S/D) feature. An interlayer dielectric (ILD) layer is placed over these S/D features, and an S/D contact is directly above them. The S/D contact makes direct contact with the first S/D feature but is isolated from the second S/D feature by the ILD layer.

Abstract

A semiconductor structure includes a first semiconductor fin and a second semiconductor fin adjacent to the first semiconductor fin. The first and the second semiconductor fins extend lengthwise along a first direction over a substrate. A metal gate structure is disposed over the first and second semiconductor fins, the metal gate structure extending lengthwise along a second direction perpendicular to the first direction. A first epitaxial source/drain (S/D) feature is disposed over the first semiconductor fin, and a second epitaxial S/D feature is disposed over the second semiconductor fin. An interlayer dielectric (ILD) layer is disposed over the first and the second epitaxial S/D features. And an S/D contact is disposed directly above the first and second epitaxial S/D features. The S/D contact directly contacts the first epitaxial S/D feature, and the S/D contact is isolated from the second epitaxial S/D feature by the ILD layer.

Integrated Fan Out Method Utilizing a Filler-Free Insulating Material (18335294)

Main Inventor

Wei-Chih Chen

Brief explanation

The abstract describes a method of creating a redistribution structure using insulating materials that have a high shrinkage rate and do not contain any filler. This allows for the achievement of good planarity without the need for planarization of each insulating layer in the structure. This simplifies the process of creating the redistribution structure.

Abstract

A redistribution structure is made using filler-free insulating materials with a high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Semiconductor Device and Method of Manufacture (18334843)

Main Inventor

Jiun Yi Wu

Brief explanation

The abstract describes a method for assembling electronic components on a carrier. The method involves creating a redistribution structure on the carrier and then attaching an integrated passive device to one side of the redistribution structure. An interconnect structure is also attached to the same side of the redistribution structure, with the integrated passive device placed between them. An underfill material is deposited between the interconnect structure and the redistribution structure. Finally, a semiconductor device is attached to the other side of the redistribution structure.

Abstract

A method includes forming a redistribution structure on a carrier, attaching an integrated passive device on a first side of the redistribution structure, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure, depositing an underfill material between the interconnect structure and the redistribution structure, and attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

SEMICONDUCTOR PACKAGE WITH RIVETING STRUCTURE BETWEEN TWO RINGS AND METHOD FOR FORMING THE SAME (18336303)

Main Inventor

Chien Hung Chen

Brief explanation

This abstract describes a semiconductor package and a method of creating it. The package includes a substrate and a semiconductor device mounted on the substrate. There are two rings, with the first one surrounding the semiconductor device and the second one placed on top of the first ring. The first ring has a protruding part on its top surface, and the second ring has a matching recessed part on its bottom surface. These parts connect the two rings together. An adhesive layer is used to attach the rings to the substrate.

Abstract

A semiconductor package and a method of forming the same are provided. The semiconductor package includes a package substrate and a semiconductor device mounted on the surface of the package substrate. A first ring is disposed over the surface of the package substrate and surrounds the semiconductor device. A second ring is disposed over the top surface of the first ring. Also, a protruding part and a matching recessed part are formed on the top surface of the first ring and the bottom surface of the second ring, respectively. The protruding part extends into and engages with the recessed part to connect the first ring and the second ring. An adhesive layer is disposed between the surface of the package substrate and the bottom surface of the first ring for attaching the first ring and the overlying second ring to the package substrate.

Semiconductor Die Connection System and Method (18332990)

Main Inventor

Ming-Fa Chen

Brief explanation

The abstract describes a system and method for connecting semiconductor dies. It explains that a first semiconductor die with a smaller width is connected to a second semiconductor die with a larger width, which is still connected to a semiconductor wafer. The first semiconductor die is then encapsulated and thinned to expose a through substrate via. The second semiconductor die is separated from the wafer, and the combined first and second semiconductor dies are connected to another substrate.

Abstract

A system and method for connecting semiconductor dies is provided. An embodiment comprises connecting a first semiconductor die with a first width to a second semiconductor die with a larger second width and that is still connected to a semiconductor wafer. The first semiconductor die is encapsulated after it is connected, and the encapsulant and first semiconductor die are thinned to expose a through substrate via within the first semiconductor die. The second semiconductor die is singulated from the semiconductor wafer, and the combined first semiconductor die and second semiconductor die are then connected to another substrate.

ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS (18210472)

Main Inventor

Yu-Hung YEH

Brief explanation

This abstract describes an electrostatic discharge (ESD) protection apparatus and the method used to create it. The apparatus includes multiple transistors patterned on a semiconductor substrate during the front-end-of-line (FEOL) process. Metal interconnects are then formed on top of these transistors during the back-end-of-line (BEOL) process to connect them. Additionally, a series of passive components are formed underneath the semiconductor substrate in a backside layer during the backside back-end-of-line (B-BEOL) process. These passive components are connected to the transistors through a series of vias.

Abstract

An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.

Semiconductor Device and Method of Manufacture (18335637)

Main Inventor

Wan-Yi Kao

Brief explanation

The abstract describes a semiconductor device and its manufacturing method. It explains that a dielectric fin is created to separate neighboring semiconductor fins. The dielectric fin is made using a deposition process, where specific deposition times and temperatures are used to enhance the resistance of the dielectric fin to subsequent etching processes.

Abstract

A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

TRANSISTOR GATE STRUCTURES AND METHODS OF FORMING THE SAME (18333981)

Main Inventor

Hsin-Yi Lee

Brief explanation

The abstract describes a device that includes two nanostructures surrounded by a gate dielectric made of dielectric materials. The device also includes a gate electrode, which consists of a work function tuning layer made of a pure work function metal. This metal, along with the dielectric materials, fills the space between the two nanostructures. The work function tuning layer is covered by an adhesion layer, and on top of that is a fill layer.

Abstract

In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.

ETCH PROFILE CONTROL OF GATE CONTACT OPENING (18329472)

Main Inventor

Te-Chih HSIUNG

Brief explanation

The abstract describes a device that includes various layers and structures. It has source/drain epitaxial structures on a substrate, source/drain contacts on top of the epitaxial structures, and a gate structure positioned between the source/drain contacts. There is a gate dielectric cap over the gate structure, which is lower than the top surfaces of the source/drain contacts. An oxide-based etch-resistant layer is placed over the gate dielectric cap, followed by a nitride-based etch stop layer. An interlayer dielectric (ILD) layer is then added over the nitride-based etch stop layer. Finally, a gate contact is created to connect with the gate structure by extending through the ILD layer, nitride-based etch stop layer, oxide-based etch-resistant layer, and gate dielectric cap.

Abstract

A device comprises source/drain epitaxial structures over a substrate; source/drain contacts over the source/drain epitaxial structures, respectively; a gate structure laterally between the source/drain contacts; a gate dielectric cap over the gate structure and having a bottom surface below top surfaces of the source/drain contacts; an oxide-based etch-resistant layer over the gate dielectric cap; a nitride-based etch stop layer over the oxide-based etch-resistant layer; an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and a gate contact extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch-resistant layer, and the gate dielectric cap to electrically connect with the gate structure.

METHOD FOR FORMING SOURCE/DRAIN CONTACTS UTILIZING AN INHIBITOR (18329126)

Main Inventor

Lin-Yu Huang

Brief explanation

This abstract describes a device that includes various components such as a substrate, isolation structure, gate structure, gate spacer, source/drain region, silicide layer, and dielectric liner. These components are arranged in a specific way, with the dielectric liner positioned above the silicide layer but spaced away from it. The arrangement is described in relation to a cross-sectional plane perpendicular to the lengthwise direction of the gate structure.

Abstract

A device includes a substrate, an isolation structure over the substrate, a gate structure over the isolation structure, a gate spacer on a sidewall of the gate structure, a source/drain (S/D) region adjacent to the gate spacer, a silicide on the S/D region, a dielectric liner over a sidewall of the gate spacer and on a top surface of the isolation structure, wherein a bottom surface of the dielectric liner is above a top surface of the silicide layer and spaced away from the top surface of the silicide layer in a cross-sectional plane perpendicular to a lengthwise direction of the gate structure.

CONTACT FORMATION METHOD AND RELATED STRUCTURE (18335741)

Main Inventor

Lin-Yu HUANG

Brief explanation

This abstract describes a semiconductor device that includes a metal gate structure with sidewall spacers. The top surface of the metal gate structure is recessed compared to the top surface of the sidewall spacers. The device also has a metal cap layer that is wider at the bottom than at the top. Additionally, there is a dielectric material on either side of the metal cap layer, with the sidewall spacers and part of the metal gate structure located beneath the dielectric material.

Abstract

A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

SEMICONDUCTOR DEVICE WITH CONFORMAL SOURCE/DRAIN LAYER (18326682)

Main Inventor

Yao-Sheng HUANG

Brief explanation

This abstract describes a semiconductor device that consists of several components. These components include a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has two parts - a top portion and a lower portion that extends from the top portion to a substrate. The gate structure spans across the semiconductor fin. The doped semiconductor layer is in contact with the top portion of the semiconductor fin. When looking at a cross-section of the device, the doped semiconductor layer has a shape that matches the shape of the top portion of the semiconductor fin.

Abstract

A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.

Finfet With Dummy Fins And Methods Of Making The Same (18332936)

Main Inventor

Chun-Hao Hsu

Brief explanation

This abstract describes a semiconductor structure that consists of a semiconductor fin and a dielectric fin. The semiconductor fin is a protrusion from a substrate and is oriented in one direction. The dielectric fin is placed over the substrate and is oriented in a direction perpendicular to the semiconductor fin. The dielectric fin acts as a sidewall for the semiconductor fin. It is made up of two layers, with the first layer being different in composition from the second layer. Lastly, there is a metal gate stack placed over the semiconductor fin, also oriented in the same direction as the dielectric fin.

Abstract

A semiconductor structure includes a semiconductor fin protruding from a substrate and oriented lengthwise along a first direction, a dielectric fin disposed over the substrate and oriented lengthwise along a second direction perpendicular to the first direction, where the dielectric fin defines a sidewall of the semiconductor fin along the second direction and where the dielectric fin includes a first dielectric layer disposed over a second dielectric layer that differs from the first dielectric layer in composition, and a metal gate stack disposed over the semiconductor fin and oriented lengthwise along the second direction.

Methods Of Forming Air Spacers In Semicondutor Devices (18336561)

Main Inventor

Chao-Hsun Wang

Brief explanation

The abstract describes a semiconductor structure that includes various components such as a source/drain feature, a metal gate stack, interlayer dielectric layers, and a contact. One notable feature of this structure is the presence of an air gap between the sidewall of the contact and one of the interlayer dielectric layers. This air gap helps to improve the performance and efficiency of the semiconductor structure.

Abstract

A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Channel Configuration for Improving Multigate Device Performance and Method of Fabrication Thereof (18190754)

Main Inventor

Chih-Ching Wang

Brief explanation

This abstract describes multi-gate devices and the methods used to fabricate them. The devices consist of a channel layer, two source/drain features, and a metal gate. The channel layer is made up of a first and second horizontal segment, connected by a vertical segment. The horizontal segments extend in one direction, while the vertical segment extends in another direction. The vertical segment is thicker than it is wide. The channel layer is positioned between the two source/drain features, and the metal gate wraps around it. In certain cases, the horizontal segments are nanosheets.

Abstract

Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

DECISION FEEDBACK EQUALIZATION EMBEDDED IN SLICER (18133976)

Main Inventor

Shu-Chun YANG

Brief explanation

The abstract describes an apparatus and method for reducing inter-symbol interference (ISI) in communication channels. It introduces a decision feedback equalizer that includes delay latches and a slicer circuit. The slicer circuit receives an input signal from the communication channel and delayed feedback signals from the delay latches. It determines the logical state of the input signal using a dynamic threshold voltage calibration circuit. This circuit regulates the current flow between the output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

Abstract

An apparatus and method for providing a decision feedback equalizer are disclosed herein. In some embodiments, a method and apparatus for reduction of inter-symbol interference (ISI) caused by communication channel impairments is disclosed. In some embodiments, a decision feedback equalizer includes a plurality of delay latches connected in series, a slicer circuit configured to receive an input signal from a communication channel and delayed feedback signals from the plurality of delay latches and determine a logical state of the received input signal, wherein the slicer circuit further comprises a dynamic threshold voltage calibration circuit configured to regulate a current flow between output nodes of the slicer circuit and ground based on the received delayed feedback signal and impulse response coefficients of the communication channel.

SRAM CELL WITH BALANCED WRITE PORT (18333197)

Main Inventor

Kuo-Hsiu Hsu

Brief explanation

This abstract describes a semiconductor device that consists of multiple active regions and gates. The active regions are divided into first, second, third, fourth, and fifth sections, each extending in one direction. The first four sections contain transistors with channel regions and source/drain regions, while the fifth section contains transistors with channel regions and source/drain regions. The gates, which extend in a perpendicular direction, are designed to connect with the channel regions of the corresponding transistors. Specifically, the first, second, and fifth gates are connected together. Additionally, the fifth active region is positioned between the second and third active regions.

Abstract

A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction. The first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected. The fifth active region is disposed between the second and third active regions.

MEMORY DEVICE WITH BOTTOM ELECTRODE (18333145)

Main Inventor

Hsia-Wei CHEN

Brief explanation

This abstract describes a memory device that consists of several components. It starts with a bottom electrode, followed by a buffer element, a metal-containing oxide portion, a resistance switch element, and finally a top electrode. The buffer element is located above the bottom electrode, while the metal-containing oxide portion is on top of the buffer element. Importantly, the metal-containing oxide portion and the buffer element are made of the same metal material. The resistance switch element is then placed over the metal-containing oxide portion, and the top electrode is the final layer on top of the resistance switch element.

Abstract

A memory device includes a bottom electrode, a buffer element, a metal-containing oxide portion, a resistance switch element, and a top electrode. The buffer element is over the bottom electrode. The metal-containing oxide portion is over the buffer element, in which the metal-containing oxide portion has a same metal material as that of the buffer element. The resistance switch element is over the metal-containing oxide portion. The top electrode is over the resistance switch element.