US Patent Application 18329472. ETCH PROFILE CONTROL OF GATE CONTACT OPENING simplified abstract
Contents
ETCH PROFILE CONTROL OF GATE CONTACT OPENING
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Te-Chih Hsiung of Taipei City (TW)
Huan-Just Lin of Hsinchu City (TW)
Jyun-De Wu of New Taipei City (TW)
ETCH PROFILE CONTROL OF GATE CONTACT OPENING - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18329472 Titled 'ETCH PROFILE CONTROL OF GATE CONTACT OPENING'
Simplified Explanation
The abstract describes a device that includes various layers and structures. It has source/drain epitaxial structures on a substrate, source/drain contacts on top of the epitaxial structures, and a gate structure positioned between the source/drain contacts. There is a gate dielectric cap over the gate structure, which is lower than the top surfaces of the source/drain contacts. An oxide-based etch-resistant layer is placed over the gate dielectric cap, followed by a nitride-based etch stop layer. An interlayer dielectric (ILD) layer is then added over the nitride-based etch stop layer. Finally, a gate contact is created to connect with the gate structure by extending through the ILD layer, nitride-based etch stop layer, oxide-based etch-resistant layer, and gate dielectric cap.
Original Abstract Submitted
A device comprises source/drain epitaxial structures over a substrate; source/drain contacts over the source/drain epitaxial structures, respectively; a gate structure laterally between the source/drain contacts; a gate dielectric cap over the gate structure and having a bottom surface below top surfaces of the source/drain contacts; an oxide-based etch-resistant layer over the gate dielectric cap; a nitride-based etch stop layer over the oxide-based etch-resistant layer; an interlayer dielectric (ILD) layer over the nitride-based etch stop layer; and a gate contact extending through the ILD layer, the nitride-based etch stop layer, the oxide-based etch-resistant layer, and the gate dielectric cap to electrically connect with the gate structure.
