US Patent Application 18336137. MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE simplified abstract
Contents
MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Yu-Hung Cheng of Tainan City (TW)
Yu-Chun Chang of Tainan City (TW)
MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18336137 Titled 'MULTILAYER ISOLATION STRUCTURE FOR HIGH VOLTAGE SILICON-ON-INSULATOR DEVICE'
Simplified Explanation
The abstract describes a new type of deep trench isolation structure for high voltage semiconductor-on-insulator devices. This structure surrounds the active region of a semiconductor-on-insulator substrate and consists of two insulator sidewall spacers with a multilayer silicon-comprising isolation structure in between. The multilayer structure includes a top polysilicon portion and a bottom silicon portion, with the bottom portion being doped with boron. The bottom polysilicon portion is formed through a selective deposition process, while the top polysilicon portion is formed through a non-selective deposition process.
Original Abstract Submitted
Deep trench isolation structures for high voltage semiconductor-on-insulator devices are disclosed herein. An exemplary deep trench isolation structure surrounds an active region of a semiconductor-on-insulator substrate. The deep trench isolation structure includes a first insulator sidewall spacer, a second insulator sidewall spacer, and a multilayer silicon-comprising isolation structure disposed between the first insulator sidewall spacer and the second insulator sidewall spacer. The multilayer silicon-comprising isolation structure includes a top polysilicon portion disposed over a bottom silicon portion. The bottom polysilicon portion is formed by a selective deposition process, while the top polysilicon portion is formed by a non-selective deposition process. In some embodiments, the bottom silicon portion is doped with boron.
