US Patent Application 18210472. ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS simplified abstract
Contents
ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Wun-Jie Lin of Hsinchu City (TW)
Jam-Wem Lee of Hsinchu City (TW)
ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS - A simplified explanation of the abstract
- This abstract for appeared for US patent application number 18210472 Titled 'ELECTRICAL PASSIVE ELEMENTS OF AN ESD POWER CLAMP IN A BACKSIDE BACK END OF LINE (B-BEOL) PROCESS'
Simplified Explanation
This abstract describes an electrostatic discharge (ESD) protection apparatus and the method used to create it. The apparatus includes multiple transistors patterned on a semiconductor substrate during the front-end-of-line (FEOL) process. Metal interconnects are then formed on top of these transistors during the back-end-of-line (BEOL) process to connect them. Additionally, a series of passive components are formed underneath the semiconductor substrate in a backside layer during the backside back-end-of-line (B-BEOL) process. These passive components are connected to the transistors through a series of vias.
Original Abstract Submitted
An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
