US Patent Application 18333197. SRAM CELL WITH BALANCED WRITE PORT simplified abstract

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SRAM CELL WITH BALANCED WRITE PORT

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.


Inventor(s)

Kuo-Hsiu Hsu of Taoyuan County (TW)


Yu-Kuan Lin of Taipei City (TW)


Feng-Ming Chang of Hsinchu County (TW)


Lien-Jung Hung of Taipei (TW)


Ping-Wei Wang of Hsin-Chu (TW)


SRAM CELL WITH BALANCED WRITE PORT - A simplified explanation of the abstract

  • This abstract for appeared for US patent application number 18333197 Titled 'SRAM CELL WITH BALANCED WRITE PORT'

Simplified Explanation

This abstract describes a semiconductor device that consists of multiple active regions and gates. The active regions are divided into first, second, third, fourth, and fifth sections, each extending in one direction. The first four sections contain transistors with channel regions and source/drain regions, while the fifth section contains transistors with channel regions and source/drain regions. The gates, which extend in a perpendicular direction, are designed to connect with the channel regions of the corresponding transistors. Specifically, the first, second, and fifth gates are connected together. Additionally, the fifth active region is positioned between the second and third active regions.


Original Abstract Submitted

A semiconductor device includes first, second, third, fourth, and fifth active regions each extending lengthwise along a first direction, and first, second, third, fourth, fifth, and sixth gates each extending lengthwise along a second direction perpendicular to the first direction. The first, second, third, and fourth active regions comprise channel regions and source/drain (S/D) regions of first, second, third, and fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The first through sixth gates are configured to engage the channel regions of the first through sixth transistors respectively. The first, second, and fifth gates are electrically connected. The fifth active region is disposed between the second and third active regions.