SAMSUNG ELECTRONICS CO., LTD. patent applications published on November 30th, 2023

Patent applications for SAMSUNG ELECTRONICS CO., LTD. on November 30th, 2023

STATION DEVICE AND OPERATING METHOD OF STATION DEVICE (18326016)

Main Inventor

Seongu LEE

Passive Breathing-Rate Determination (18198989)

Main Inventor

Tousif Ahmed

SEMICONDUCTOR DEVICE MEASUREMENT METHOD USING X-RAY SCATTERING AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD INCLUDING THE MEASUREMENT METHOD (18095926)

Main Inventor

Jaeyong LEE

SYSTEM AND METHOD FOR DEEP AUDIO SPECTRAL PROCESSING FOR RESPIRATION RATE AND DEPTH ESTIMATION USING SMART EARBUDS (18314643)

Main Inventor

Mohsin Yusuf Ahmed

GENE AMPLIFICATION CHIP, APPARATUS FOR GENE AMPLIFICATION, AND APPARATUS FOR BIO-PARTICLE ANALYSIS (17954559)

Main Inventor

Jae Hong LEE

POLISHING PAD AND SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME (18100937)

Main Inventor

Donghoon KWON

CLEANING COMPOSITION FOR REMOVING RESIDUES ON SURFACE, METHOD OF CLEANING METAL-CONTAINING FILM BY USING THE SAME, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE BY USING THE SAME (18324260)

Main Inventor

Byungjoon Kang

VARIANT OF NITROUS OXIDE REDUCTASE PROTEIN AND METHOD OF REDUCING CONCENTRATION OF NITROUS OXIDE IN SAMPLE (18318262)

Main Inventor

Woo Yong Shim

COOKING APPARATUS (18231075)

Main Inventor

Sangjin KIM

REFRIGERATOR (18232997)

Main Inventor

Chomin LEE

INSPECTION METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE USING THE SAME (18097924)

Main Inventor

Donghyun LEE

INSPECTION SYSTEM OF SEMICONDUCTOR WAFER AND METHOD OF DRIVING THE SAME (18446837)

Main Inventor

Doyoung YOON

METHOD AND APPARATUS WITH BATTERY PARAMETERS DETERMINATION (18319116)

Main Inventor

Sagar BHARATHRAJ

METHOD AND DEVICE WITH BATTERY SHORT CIRCUIT DETECTION (18074969)

Main Inventor

Sagar BHARATHRAJ

APPARATUS AND METHOD FOR POWER SAVING IN GESTURE RECOGNITION USING MMWAVE RADAR (18068513)

Main Inventor

Priyabrata Parida

ELECTRONIC DEVICE FOR DETERMINING LOCATION OF EXTERNAL ELECTRONIC DEVICE, AND OPERATION METHOD OF ELECTRONIC DEVICE (18450120)

Main Inventor

Hyunchul KIM

CAMERA MODULE AND ELECTRONIC DEVICE HAVING SAME (18333142)

Main Inventor

Sungmin KIM

LENS ASSEMBLY AND ELECTRONIC DEVICE COMPRISING SAME (18113327)

Main Inventor

Yongjae LEE

LENS ASSEMBLY AND ELECTRONIC DEVICE INCLUDING SAME (18156799)

Main Inventor

Yongjae LEE

DISPLAY APPARATUS AND LIGHT SOURCE APPARATUS THEREOF (18118979)

Main Inventor

Chunsoon Park

SUBSTRATE WEIGHT MEASUREMENT APPARATUS, A SUBSTRATE PROCESSING APPARATUS INCLUDING THE SAME, AND A METHOD OF PROCESSING A SUBSTRATE USING THE SUBSTRATE PROCESSING APPARATUS (18076591)

Main Inventor

Sangjine PARK

HINGE MODULE AND ELECTRONIC DEVICE COMPRISING SAME (18232480)

Main Inventor

Giyun LEE

ELECTRONIC DEVICE COMPRISING MICROPHONE MODULE (18448469)

Main Inventor

Hyunjoong YOON

ELECTRONIC DEVICE COMPRISING HINGE MODULE (18231550)

Main Inventor

Jungjin KIM

SERVER DEVICE CAPABLE OF BEING STABLY OPERATED IN SPITE OF POWER LOSS AND METHOD OF OPERATING THE SAME (18167263)

Main Inventor

Sung Chul HUR

STORAGE DEVICE PREVENTING LOSS OF DATA IN SITUATION OF LACKING POWER AND OPERATING METHOD THEREOF (18305474)

Main Inventor

Soo-Young JI

ELECTRONIC DEVICE, AND METHOD FOR CONTROLLING ELECTRONIC DEVICE (17892499)

Main Inventor

Hejung YANG

ELECTRONIC DEVICE FOR RECEIVING AND DISPLAYING APPLICATION SCREEN FROM EXTERNAL DEVICE AND METHOD FOR CONTROLLING SAME (18202710)

Main Inventor

Huijun SHIM

METHOD AND SYSTEM FOR MANAGING MEMORY ASSOCIATED WITH A PERIPHERAL COMPONENT INTERCONNECT EXPRESS (PCIE) SOLID-STATE DRIVE (SSD) (17867742)

Main Inventor

Krishna Kanth Reddy

STORAGE SYSTEM INCLUDING BATTERY MODULE AND METHOD FOR OPERATING THE SAME (18135141)

Main Inventor

SEUNGHAN LEE

STORAGE DEVICE PREVENTING LOSS OF DATA IN SITUATION OF LACKING POWER AND OPERATING METHOD THEREOF (18196671)

Main Inventor

Soo-Young JI

MEMORY CONTROLLER SEARCHING FOR DATA INPUT/OUTPUT VOLTAGE, MEMORY SYSTEM, AND OPERATING METHOD OF THE MEMORY SYSTEM (18310959)

Main Inventor

Byungwook So

STORAGE DEVICE PROVIDING HIGH PURGE PERFORMANCE AND MEMORY BLOCK MANAGEMENT METHOD THEREOF (18124821)

Main Inventor

Youngjoon Jang

STORAGE SYSTEM AND OPERATION METHOD THEREFOR (18141007)

Main Inventor

Wonseb JEONG

VIRTUAL COMPUTATIONAL STORAGE DEVICES (18229902)

Main Inventor

Gayathiri Venkataraman

NETWORK STORAGE GATEWAY (18231241)

Main Inventor

Yang Seok KI

METHOD AND APPARATUS WITH REPEATED MULTIPLICATION (18187971)

Main Inventor

Ho Young KIM

SYSTEM AND METHOD TO ENHANCE LAUNCHING OF APPLICATION AT A USER EQUIPMENT (18334997)

Main Inventor

Sripurna Mutalik

APPARATUS AND METHOD FOR SIMULATION AUTOMATION IN REGRESSION TEST (18198577)

Main Inventor

Jicheon Kim

Brief explanation

The patent application describes a method for simulating an integrated circuit using a simulation tool. 

• The method involves providing a test case to the simulation tool and obtaining simulation results and logs from the tool.
• A machine learning model is used to classify the test case into a specific fail class out of multiple fail classes.
• A controller then applies a solution to the test case, generating a renewed test case.
• The renewed test case is then provided back to the simulation tool for further testing.

Abstract

A method of simulating an integrated circuit includes providing at least one test case to a simulation tool, obtaining at least one first simulation result and at least one first simulation log from the simulation tool, classifying, with a first machine learning model, the at least one test case into one fail class of a plurality of fail classes, generating at least one renewed test case by applying, with a controller, a solution to the at least one test case, and providing the at least one renewed test case to the simulation tool.

INPUT OUTPUT MEMORY MANAGEMENT UNIT AND ELECTRONIC DEVICE HAVING THE SAME (18101352)

Main Inventor

Youngseok KIM

Brief explanation

The patent application describes an input output memory management unit (IOMMU) that manages memory translation for efficient data access.

• The IOMMU includes a first memory device with a translation lookaside buffer (TLB) and a second memory device with a translation group table.
• Multiple translation request controllers are present to perform address translation operations.
• An allocation controller is responsible for handling incoming requests and allocating the appropriate translation request controller.
• When a request is received, the allocation controller first checks the TLB using the page table identifier (ID) and virtual page number.
• If there is a TLB miss, the allocation controller then looks up the translation group table using the page table ID and virtual page number.
• Based on the translation group table miss, the allocation controller selects the appropriate translation request controller for the request.

Abstract

Disclosed is an input output memory management unit (IOMMU) including a first memory device including a translation lookaside buffer (TLB), a second memory device including a translation group table, a plurality of translation request controllers, each of which is configured to perform an address translation operation, and an allocation controller. The allocation controller may be configured to receive a first request including a first page table identifier (ID), a first virtual page number, and a first page offset, looks up the TLB by using the first page table ID and the first virtual page number, look up the translation group table by using the first page table ID and the first virtual page number when a TLB miss for the first request occurs, and allocate a first translation request controller among the plurality of translation request controllers based on a translation group table miss for the first request.

STORAGE DEVICE ADJUSTING DATA RATE AND STORAGE SYSTEM INCLUDING THE SAME (18446670)

Main Inventor

Jeongsu KIM

Brief explanation

- The patent application describes a method for operating a storage device.

- The method involves receiving a request from a host to change the data rate. - The request is received through an input signal pin. - The storage device sends a response to the host indicating whether the data rate can be changed. - The response is sent through an output signal pin at the current data rate. - The data rate is changed to a new rate based on whether a tail-of-burst (TOB) signal is outputted. - The TOB signal indicates the end of the response sequence. - The method allows for efficient and controlled data rate changes in the storage device.

Abstract

A method of operating a storage device includes receiving a first bit sequence including a request for changing a data rate from a host according to a first data rate through an input signal pin; sending a second bit sequence including a response to the request for changing a data rate to the host at the first data rate through an output signal pin; and changing the data rate to a second data rate according to whether a tail-of-burst (TOB) indicating an end of the second bit sequence is output.

DEVICE, METHOD, AND COMPUTER PROGRAM FOR PERFORMING ACTIONS ON IOT DEVICES (18449345)

Main Inventor

Siba Prasad SAMAL

Brief explanation

This patent application describes a method for controlling an Internet of Things (IoT) device using an electronic device. Here are the key points:

• The method involves obtaining input from a user that corresponds to a predefined action.
• If the input is not identifiable, it is transmitted to a server.
• The server provides information about activities mapped to IoT devices based on the input, as well as information about objects and/or context.
• The method then identifies the appropriate action to be performed on an IoT device based on the correlation between the input and the mapped activities.

Abstract

A method of controlling an Internet of Things (IoT) device to perform an action, is performed by an electronic device and includes obtaining at least one input from a user, based on a predefined action corresponding to the obtained at least one input being not identifiable, transmitting the obtained at least one input to a server, receiving, from the server, information regarding at least one activity that is mapped to at least one IoT device that is identified based on the transmitted at least one input, and information regarding at least one object and/or at least one context, and identifying an action to be performed on an IoT device among the at least one IoT device, based on a correlation between the obtained at least one input and the at least one activity mapped to the at least one IoT device.

STORAGE DEVICE WITH CONCURRENT INTIALIZATION AND FINGERPRINT RECOGNITION (18365021)

Main Inventor

YOUNGJIN PARK

Brief explanation

The abstract describes a method for operating a storage device with biometric security protection. Here is a simplified explanation of the abstract:

• The method involves starting both a device initialization operation and a biometric recognition operation at the same time.
• If the device initialization operation is completed and the biometric recognition operation is successful, the storage device is set to a normal access mode.
• The normal access mode allows external access to the storage device based on the biometric security protection.
• The device initialization operation and the biometric recognition operation are performed concurrently.

Bullet points explaining the patent/innovation:

• The method allows for simultaneous initialization and biometric recognition operations on a storage device.
• This ensures that the device is ready for use while also verifying the user's biometric information.
• If both operations are successful, the storage device is set to a normal access mode.
• The normal access mode allows external access to the storage device, but only if the biometric recognition is successful.
• Performing the initialization and biometric recognition operations concurrently saves time and improves efficiency.

Abstract

A method is provided for operating a storage device having biometric security protection, including: simultaneously starting both a device initialization operation and a biometric recognition operation; and if the device initialization operation has completed and the biometric recognition operation has successfully completed, setting the storage device to a normal access mode permitting external access to the storage device in accordance with the biometric security protection, wherein the device initialization operation and the biometric recognition operation are performed concurrently.

TEMPERATURE MARGIN SETTING METHOD FOR 3D INTEGRATED CIRCUIT (18061636)

Main Inventor

Ki-Ok Kim

Brief explanation

- The patent application describes a method for designing a 3D integrated circuit.

- The method involves generating a distance-delay table based on a thermal analysis result. - The first timing path distance is calculated for the first chip in a 3D signal transfer path. - The second timing path distance is calculated for the second chip in the 3D signal transfer path. - The 3D timing path distance is calculated by summing the first and second timing path distances. - A temperature margin for the 3D timing path is set based on the distance-delay table and the 3D timing path distance.

Abstract

A method of designing a 3D integrated circuit includes generating a distance-delay table with respect to at least one of a first chip or a second chip stacked on the first chip, based on a thermal analysis result, calculating a first timing path distance with respect to a first timing path corresponding to the first chip in a 3D signal transfer path, calculating a second timing path distance with respect to a second timing path corresponding to the second chip in the 3D signal transfer path, calculating a 3D timing path distance by summing the first timing path distance and the second timing path distance, and setting a temperature margin with respect to a 3D timing path based on the distance-delay table and the 3D timing path distance.

SYSTEM AND METHOD FOR CONTEXT INSERTION FOR CONTRASTIVE SIAMESE NETWORK TRAINING (18315931)

Main Inventor

Brendon Christopher Beachy Eby

Brief explanation

- The patent application describes a method for processing input utterances that are continuations of previous utterances.

- The method involves using a trained Siamese network to determine embeddings (representations) of tokens from the input utterance. - These embeddings are then combined with a context token embedding representing the class associated with the previous utterance to generate a representative embedding for the input utterance. - The method also involves determining representative embeddings for multiple possible classes, where each class has first and second threshold boundaries. - Using the Siamese network, similarity scores are calculated for each possible class based on the distance between the representative input utterance embedding and a selected threshold boundary of the representative embedding for that class. - Based on the similarity scores, a class is identified for the input utterance, and an action corresponding to the identified class is performed.

Abstract

A method includes receiving an input utterance that is a continuation of a previous utterance. The method also includes, using a trained Siamese network, determining input utterance embeddings representing tokens from the input utterance, pooling the input utterance embeddings with a context token embedding representing a class associated with the previous utterance to generate a representative input utterance embedding, and determining a representative embedding associated with each of multiple possible classes. Each possible class is associated with first and second threshold boundaries. The method further includes, using the trained Siamese network, determining a similarity score for each possible class based on a distance between the representative input utterance embedding and a selected threshold boundary of the representative embedding for that possible class and identifying a class for the input utterance based on the determined similarity scores. In addition, the method includes performing an action corresponding to the identified class.

METHOD AND ELECTRONIC DEVICE FOR TILT CORRECTION OF VIDEO (18343589)

Main Inventor

Debi Prasanna MOHANTY

Brief explanation

The patent application describes a method for correcting the tilt of a video captured by an electronic device. Here are the key points:

• The method starts by receiving a user-selected video.
• It identifies a sequence of image frames that represent a scene in the video.
• The degree of tilt in each image frame is determined.
• An Artificial Intelligence (AI) model is used to analyze the degree of tilt in each frame and determine if it is unintentional.
• If the cause of tilt is determined to be unintentional, the method performs tilt correction on the sequence of image frames.

Abstract

A method for tilt correction of a video by an electronic device. The method may include receiving a user selection of the video. The method may include identifying a sequence of image frames of the video representing a scene in the video. The method may include determining a degree of tilt in each image frame of the sequence of image frames. The method may include determining whether cause of tilt in the sequence of image frames is un-intentional by analyzing the degree of tilt in each image frame using a trained Artificial Intelligence (AI) model. The method may include performing the tilt correction on the sequence of image frames based on the cause of tilt being un-intentional.

ELECTRONIC APPARATUS AND IMAGE PROCESSING METHOD THEREOF (18195516)

Main Inventor

Hyungrae Kim

Brief explanation

The patent application describes an electronic apparatus that uses a memory and a processor to process depth information and generate images based on that information.

• The apparatus obtains depth information of two consecutive image frames.
• It calculates the difference between the two image frames.
• The apparatus then applies weights to the depth information of each frame to generate final depth information for the second image frame.
• Based on this final depth information, the apparatus generates an image related to the second image frame.

Abstract

An electronic apparatus includes a memory and a processor that obtains second depth information of a second image frame subsequent to the first image frame, obtains an image difference value between the first image frame and the second image frame, obtains final depth information corresponding to a second image frame by applying a first weight and a second weight to a first depth information and a second depth information, respectively, and generates an image related to the second image frame based on the obtained final depth information.

ELECTRONIC DEVICE AND METHOD FOR IMPROVING FAR-FIELD PERFORMANCE OF CAMERA (18448575)

Main Inventor

Yongchan KEH

Brief explanation

The patent application describes an electronic device with an optical output module and an image sensor.

• The device can output a spotlight and a floodlight at different times.
• It can capture reflected light from these lights using the image sensor to obtain image data.
• The device has a memory and a processor that controls the optical output module, image sensor, and memory.
• The processor can generate depth maps based on the image data from the spotlight and floodlight.
• The depth maps provide information about the distance of objects in the captured images.
• The processor can also combine the depth maps to produce a more accurate depth map.

Abstract

An electronic device is provided. The electronic device includes an optical output module, an image sensor configured to receive a reflected light that originates from a light output by the optical output module, and to obtain image data, a memory, and a processor operatively coupled to the optical output module, the image sensor, and the memory, wherein the processor is configured to control the optical output module to output a spotlight at a first time point, control the optical output module to output a floodlight at a second time point, produce a first depth map based on first image data associated with a first reflected light that originates from the spotlight, produce a second depth map based on second image data associated with a second reflected light that originates from the floodlight, and produce a third depth map based on the first depth map and the second depth map.

SERVER, USER TERMINAL, AND SERVICE PROVIDING METHOD, AND CONTROL METHOD THEREOF (18234219)

Main Inventor

Woo-Yong CHANG

Brief explanation

The patent application describes a system that includes an electronic device and a server.

• The electronic device has a display, a communicator, and a controller.
• The device can transmit location data to the server.
• The server has a communicator and a controller.
• The server can receive the location data and identify a course of travel.
• The server can link photograph images to locations on the course of travel.
• The server can transmit the course of travel and photograph images back to the electronic device.
• The electronic device can receive the course of travel and photograph images.
• The device can display a map image, the course of travel, and the photograph images simultaneously on the display.
• The photograph images are linked to specific locations on the course of travel.

Abstract

An example system includes an electronic device and a server. The electronic device includes a display; a first communicator; and a first controller configured to: control to transmit, to the server, location data identifying locations of the electronic device. The server includes a second communicator; and a second controller configured to: control to receive the location data; identify a course of travel; link photograph images to locations on the course of travel; and control to transmit to the electronic device the course of travel and the photograph images. The first controller of the electronic device is configured to control to receive the course of travel and the photograph images and to control to display on the display, at the same time, a map image, the course of travel, and one or more of the photograph images linked to a selected location on the course of travel.

IMAGE SIGNAL PROCESSING METHOD USING NEURAL NETWORK MODEL AND COMPUTING APPARATUS FOR PERFORMING THE SAME (18224756)

Main Inventor

Chaeeun LEE

Brief explanation

- The patent application describes a method for processing images using a neural network model.

- The method involves obtaining an image captured by an image sensor. - The shooting context of the image is identified. - A neural network model is selected based on the shooting context. - The selected neural network model is used to process the image. - The method can be used for image reconstruction or image correction. - The innovation lies in the ability to select a neural network model based on the shooting context, which can improve the processing of the image.

Abstract

A method of processing an image by using a neural network model includes obtaining an image captured via an image sensor, identifying a shooting context of the image, selecting a neural network model included in at least one of an image reconstruction module or an image correction module according to the shooting context, and processing the image by using the selected neural network model.

ELECTRONIC DEVICE, OPERATING METHOD OF ELECTRONIC DEVICE, AND RECORDING MEDIUM (18446833)

Main Inventor

Heetak CHUNG

Brief explanation

The patent application describes an electronic device that can recognize and store feature points of different individuals.

• The device has a communication circuit, memory, and at least one processor.
• The processor can store feature points of multiple people in the memory.
• It can acquire an image and identify the face of at least one person in the image.
• The device can extract a feature point related to the recognized face.
• It checks if this feature point matches any stored feature points in the memory.
• If no match is found, it transmits the feature point and related information to an external device.
• The external device stores the feature point and sends identification information back to the device.
• The device stores this identification information and can transmit the original image to the external device.

Abstract

An example electronic device includes a communication circuit; a memory; and at least one processor. The at least one processor may be configured to store a plurality of feature points corresponding to a plurality of persons in the memory; acquire a first image; acquire a first portion in which the face of at least one person is recognized in the first image; acquire a first feature point related to the face from the first portion; identify whether a second feature point corresponding to the first feature point is present in the plurality of feature points stored in the memory; and, based on no feature point corresponding to the first feature point being identified, transmit the first feature point and information related to the first feature point to an external electronic device; based on the feature point corresponding to the feature point related to the face being stored in the external electronic device, receive identification information of the external electronic device from the external electronic device,; store the received identification information; and transmit the first image to the external electronic device.

DISPLAY APPARATUS AND CONTROL METHOD THEREOF (18230818)

Main Inventor

Seungho PARK

Brief explanation

The patent application describes a display apparatus that can display moving trajectories on a display screen.

• The display apparatus includes a display, a memory, and a processor.
• The memory stores information about multiple moving trajectories.
• The processor controls the display to show a specific pixel that is shifted according to a first moving trajectory in a set of image frames.
• Once the specific pixel has completed its movement according to the first trajectory, the processor moves it by pixel units in either the vertical or horizontal direction.
• The display then shows the specific pixel shifted according to a second moving trajectory in another set of image frames.

Abstract

A display apparatus including a display, a memory configured to store moving trajectory information related to a plurality of moving trajectories. and a processor configured to control the display to display a specific pixel which is pixel-shifted according to a first moving trajectory among the plurality of moving trajectories in a plurality of image frames included in a first frame interval. The processor, based on completing of the specific pixel being pixel-shifted according to the first moving trajectory, moves the specific pixel located at a starting point of the first moving trajectory by pixel units in any one of a vertical direction and a horizontal direction, and control the display to display the specific pixel by being pixel-shifted according to a second moving trajectory among the plurality of moving trajectories in a plurality of image frames included in a second frame interval.

SYSTEM AND METHOD FOR DETECTING UNHANDLED APPLICATIONS IN CONTRASTIVE SIAMESE NETWORK TRAINING (18303394)

Main Inventor

Brendon Christopher Beachy Eby

Brief explanation

The patent application describes a method for classifying input utterances using a language model and updating the model based on the classification results.

• The method involves determining target embedding vectors for each class and generating an utterance embedding vector using a pre-trained language model.
• The predicted class for an input utterance is obtained by comparing the distances of the utterance embedding vector to spatial parameters representing the classes.
• The spatial parameters are based on the target embedding vectors associated with each class.
• The parameters of the language model are updated based on the difference between the predicted class and the expected class.

Abstract

A method includes determining, using at least one processing device of an electronic device, a target embedding vector for each class of a plurality of classes. The method also includes generating, using the at least one processing device, an utterance embedding vector using a pre-trained language model, where the utterance embedding vector represents an input utterance associated with an expected class. The method further includes obtaining, using the at least one processing device, a predicted class associated with the input utterance based on distances of the utterance embedding vector to spatial parameters representing the plurality of classes, where the spatial parameter of each class is based on the target embedding vector associated with that class. In addition, the method includes updating, using the at least one processing device, parameters of the language model based on a difference between the predicted class and the expected class.

METHOD AND VOICE ASSISTANCE APPARATUS FOR PROVIDING AN INTELLIGENCE RESPONSE (18231660)

Main Inventor

Vinay Vasanth PATAGE

Brief explanation

The patent application describes a method and apparatus for an intelligent voice response at a voice assistant device. Here is a simplified explanation of the abstract:

• The method involves a voice assistant device receiving a voice input from a user.
• While obtaining the voice input, the device also identifies non-speech input.
• The device then determines a correlation between the voice input and the non-speech input.
• Based on this correlation, the device generates a response that can be an action related to the correlation or a suggestion related to the correlation.

Bullet points explaining the patent/innovation:

• The invention focuses on improving the voice response capabilities of a voice assistant device.
• It allows the device to not only understand the user's voice input but also identify any non-speech input that may be relevant.
• By determining a correlation between the voice input and the non-speech input, the device can provide a more intelligent and context-aware response.
• The response generated by the device can be an action that is directly related to the correlation, or it can be a suggestion that is relevant to the correlation.
• This innovation enhances the overall user experience with voice assistant devices by providing more personalized and helpful responses.

Abstract

Provided are a method and an apparatus for providing an intelligent voice response at a voice assistant device. The method includes obtaining, by a voice assistant device, a voice input from a user, identifying non-speech input while obtaining the voice input, determining a correlation between the voice input and the non-speech input, and generating, based on the correlation, a response comprising an action related to the correlation or a suggestion related to the correlation.

DEVICE OF GENERATING REFERENCE VOLTAGES FOR MULTI-LEVEL SIGNALING AND MEMORY SYSTEM INCLUDING THE SAME (18151784)

Main Inventor

Sang-Hoon KIM

Brief explanation

The patent application describes a device that generates reference voltages for multi-level signaling in data communication.

• The device includes a noise information generation circuit that generates power noise information based on power noises generated by two electronic devices.
• The power noises are propagated through a communication line from the first electronic device to the second electronic device.
• The device also includes a reference voltage generation circuit that generates three or more reference voltages based on the power noise information.
• The second electronic device uses these reference voltages for data communication using a multi-level signaling scheme.

Abstract

A reference voltage generation device includes a noise information generation circuit configured to generate power noise information based on a first power noise and a second power noise, the first power noise and the second power noise generated based on a first power and a second power supplied to a first electronic device and propagated from the first electronic device to a second electronic device through a communication line, and the first electronic device and the second electronic device configured to perform data communication using a multi-level signaling scheme. The device includes a reference voltage generation circuit configured to generate three or more reference voltages for the multi-level signaling scheme based on the power noise information, and the second electronic device is configured to use the three or more reference voltages.

METHODS OF OPERATING A NEAR MEMORY PROCESSING-DUAL IN-LINE MEMORY MODULE (NMP-DIMM) FOR PERFORMING A READ OPERATION AND AN ADAPTIVE LATENCY MODULE AND A SYSTEM THEREOF (17974940)

Main Inventor

Sachin Suresh Upadhya

Brief explanation

The patent application describes a method for operating a NMP-DIMM system, which is a type of memory system.

• The method involves determining a synchronized read latency value for performing a read operation in the NMP-DIMM system.
• This value is determined based on read latency values associated with memory units in the system.
• The method also involves synchronizing data paths in the NMP-DIMM system based on the determined synchronized read latency value.

Abstract

A method of operating a Near Memory Processing-Dual In-line Memory (NMP-DIMM) system, the method including: determining, by an adaptive latency module of the NMP-DIMM system, a synchronized read latency value for performing a read operation upon receiving a Multi-Purpose Register (MPR) read instruction from a host device communicatively connected with the NMP-DIMM system, wherein the MPR read instruction is received from the host device for training the NMP-DIMM system, wherein the synchronized read latency value is determined based on one or more read latency values associated with one or more memory units of the NMP-DIMM system; and synchronizing, by the adaptive latency module, one or more first type data paths and a second type data path in the NMP-DIMM system based on the determined synchronized read latency value.

MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE (18449864)

Main Inventor

Yongsung CHO

Brief explanation

The patent application describes a memory device with a memory cell array and various components for data storage and retrieval.

• The memory device includes memory cells, data latches, a sensing latch, a temporary storage node, a switch, a first precharge circuit, and a control logic circuit.
• The data latches are connected to a sensing node and store data in a specific memory cell.
• The sensing latch is connected to the sensing node and serves as a temporary storage for data.
• The switch is connected between the sensing latch and the temporary storage node and operates based on a setup signal.
• The first precharge circuit selectively precharges a specific bit line based on the level of the temporary storage node.
• The control logic circuit controls the transfer of data between the data latches, sensing latch, and temporary storage node.
• During a dump operation, the control logic circuit transfers data from the data latches to the sensing latch while the first precharge circuit precharges the specific bit line.

Abstract

Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.

OPERATING METHOD OF MEMORY DEVICE FOR EXTENDING SYNCHRONIZATION OF DATA CLOCK SIGNAL, AND OPERATING METHOD OF ELECTRONIC DEVICE INCLUDING THE SAME (18447950)

Main Inventor

JIN-HOON JANG

Brief explanation

The patent application describes a method for a memory device to communicate with a memory controller.

• The memory device receives a command from the memory controller to synchronize a data clock signal.
• The command also defines a specific section of the clock signal for synchronization.
• The memory device prepares for the synchronization by toggling the data clock signal during a preparation time period.
• It then processes a first data stream based on the toggling of the data clock signal at a reference frequency.
• Additionally, it processes a second data stream based on the toggling of the data clock signal at the reference frequency, but extended for a period of time defined by the first clock section.

Abstract

Disclosed is an operating method of a memory device communicating with a memory controller, which includes receiving a first command from the memory controller, the first command indicating initiation of synchronization of a data clock signal and defining a clock section corresponding to the synchronization, preparing a toggling of the data clock signal during a preparation time period, processing a first data stream based on the data clock signal toggling at a reference frequency, and processing a second data stream based on the data clock toggling at the reference frequency and extended for a period of the defined first clock section.

MEMORY DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD OF ELECTRONIC DEVICE (18127980)

Main Inventor

Byungwook SO

Brief explanation

The patent application describes an operating method for an electronic device.

• The method involves performing command bus training on a command/address line between a memory device and a system-on-chip (SoC).
• It also includes performing first read training based on a first pattern stored in a mode register within the memory device.
• The method further involves performing first write training based on a first write operation on a buffer within the memory device.
• Additionally, it includes performing second read training based on a second pattern stored in a memory bank within the memory device.
• Lastly, the method involves performing second write training based on a second write operation on the memory bank.

Abstract

An operating method of an electronic device includes performing command bus training on a command/address line between a memory device and a system-on-chip (SoC), performing first read training based on a first pattern that is stored in a mode register included in the memory device, performing first write training based on a first write operation on a buffer included in the memory device, performing second read training based on a second pattern that is stored in a memory bank included in the memory device, and performing second write training based on a second write operation on the memory bank.

Non-Volatile Memory Device and Method of Operating the Same (18450241)

Main Inventor

Dong-Hun Kwak

Brief explanation

The patent application describes a method for operating a non-volatile memory device.

• The method involves performing a sensing operation on the memory device during a specific time period.
• The sensing operation is divided into three sections.
• Different voltage levels are applied to selected word lines in each section.
• The voltage level in the first section is variable based on a target voltage level.
• The voltage level in the second section is different from the first section.
• The voltage level in the third section is different from the second section.
• The first voltage level increases as the target voltage level increases.

Abstract

A method of operating a non-volatile memory device includes performing a first sensing operation on the non-volatile memory device during a first sensing time including a first section, a second section, and a third section. The performing of the first sensing operation includes applying a first voltage level, which is variable according to a first target voltage level, to a selected word line in the first section, applying a second voltage level, which is different from the first voltage level, to the selected word line in the second section, and applying the first target voltage level, which is different from the second voltage level, to the selected word line in the third section. The first voltage level becomes greater as the first target voltage level becomes greater.

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM (18365868)

Main Inventor

Taekwoon Kim

Brief explanation

The patent application describes a memory system consisting of a memory module and a memory controller.

• The memory module contains data chips that store data and are divided into two sub-channels, each generating a different code word.
• These code words are used to fill a single cache line.
• The memory controller is responsible for managing the memory system.
• If a data chip fails, the memory controller detects it and copies the data from the failed chip to an ECC (Error Correction Code) chip.
• The memory controller then releases the mapping between the failed chip and the corresponding I/O (Input/Output) and establishes a new mapping between the ECC chip and the corresponding I/O pins.

Abstract

A memory system includes a memory module and a memory controller. The memory module includes data chips that store data and are assigned to a first sub-channel that generates a first code word or a second sub-channel that generates a second code word, where the first code word and the second code are used to fill a single cache line. The memory controller, upon detection of a hard-fail data chip among the data chips, copies data from the hard-fail data chip to the ECC chip, releases mapping between the hard-fail data chip and corresponding I/O, and defines new mapping between the ECC chip and the corresponding I/O pins.

METHODS FOR REAL-TIME REPAIRING OF MEMORY FAILURES CAUSED DURING OPERATIONS, MEMORY SYSTEMS PERFORMING REPAIRING METHODS, AND DATA PROCESSING SYSTEMS INCLUDING REPAIRING MEMORY SYSTEMS (18124733)

Main Inventor

Yoonyul Yoo

Brief explanation

- The patent application describes a method for operating a memory controller that controls a memory device with a memory region and a repair memory region.

- The method involves receiving an address and associated data from the memory region in a read command. - The received data is decoded using an error correction code and any errors in the data are detected. - Error type information is generated to indicate the type of error found in the data. - A count value associated with the address is updated based on the error type information, representing the number of times that specific error has occurred for that address. - The count value is compared to a threshold value. - If the count value is equal to the threshold value, the data stored in the memory region associated with the address is backed up to the repair memory region.

Abstract

An operating method of a memory controller that controls an operation of a memory device that includes a memory region and a repair memory region. The operating method may include receiving an address associated with the memory region that is included in a first read command and data read out from the memory region associated with the address, decoding the data using an error correction code and detecting an error included in the data, generating error type information indicating a type of an error included in the data, updating, based on the error type information, a count value associated with the address, the count value indicating a number of times that the type of error indicated by the error type information has occurred for the address, comparing the count value with a threshold value, and backing up the data that is stored in the memory region associated with the address to the repair memory region when the count value is equal to the threshold value.

NEUROMORPHIC DEVICE (18204020)

Main Inventor

Youngnam HWANG

Brief explanation

- The patent application describes a neuromorphic device that includes a memory cell array and an analog to digital converter (ADC) circuit.

- The memory cell array consists of different types of resistive memory cells connected to various lines. - The first resistive memory cells store data related to the weight of a neural network. - The memory cell array can generate multiple read currents based on input signals and the stored data. - The ADC circuit is responsible for converting the read currents into digital signals.

Abstract

A neuromorphic device includes a memory cell array including first resistive memory cells connected to word lines, bit lines and source lines, second resistive memory cells connected to the word lines, at least one redundancy bit line and at least one redundancy source line, third resistive memory cells connected to at least one redundancy word line, the bit lines and the source lines. The memory cell array stores data corresponding to a weight of a neural network in the first resistive memory cells, and is configured to generate a plurality of read currents based on input signals and the data. The neuromorphic device further includes an analog to digital converter (ADC) circuit configured to convert the plurality of read currents into a plurality of digital signals.

METHOD FOR FORMING PHOTORESIST PATTERN AND METHOD FOR FORMING PATTERN ON A SUBSTRATE (18125936)

Main Inventor

Gyeyoung Kim

Brief explanation

The patent application describes a method for forming a photoresist pattern on a substrate by using a silicon oxide layer. 

• The method involves forming a first photoresist pattern on the silicon oxide layer, which is in contact with the substrate.
• The substrate with the first photoresist pattern is then subjected to entire-surface exposure.
• After the exposure, the first photoresist pattern is removed by developing it.
• Finally, a second photoresist pattern is formed on the silicon oxide layer.

This method allows for the precise formation of a photoresist pattern on a substrate, improving the overall quality and accuracy of the pattern.

Abstract

Provided is a method for forming a photoresist pattern, in which a silicon oxide layer is formed on a substrate. A first photoresist pattern, which contacts the silicon oxide layer, is formed on the silicon oxide layer. Entire-surface exposure is performed on the substrate on which the first photoresist pattern having a defect is formed. The first photoresist pattern is entirely removed by developing the first photoresist pattern, which has been subject to the entire-surface exposure. In addition, a second photoresist pattern is formed on the silicon oxide layer.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME (18067060)

Main Inventor

Jiyoung Park

Brief explanation

The patent application describes a semiconductor package that includes a semiconductor chip on a redistribution substrate.

• The semiconductor package consists of a body, a chip pad, and a pillar on the chip pad.
• It also includes a connection substrate with base layers and a lower pad on the bottom surface.
• A first passivation layer is present between the semiconductor chip and the redistribution substrate.
• A dielectric layer is placed between the redistribution substrate and the connection substrate.
• The first passivation layer and the dielectric layer are made of different materials.
• The bottom surfaces of the pillar, first passivation layer, molding layer, lower pad, and dielectric layer are all coplanar with each other.

Abstract

A semiconductor package includes a semiconductor chip on a redistribution substrate and including a body, a chip pad on the body, and a pillar on the chip pad, a connection substrate including base layers and a lower pad on a bottom surface of a lowermost one of the base layers, a first passivation layer between the semiconductor chip and the redistribution substrate, and a dielectric layer between the redistribution substrate and the connection substrate. The first passivation layer and the dielectric layer include different materials from each other. A bottom surface of the pillar, a bottom surface of the first passivation layer, a bottom surface of a molding layer, a bottom surface of the lower pad, and a bottom surface of the dielectric layer are coplanar with each other.

SEMICONDUCTOR DEVICE (18201995)

Main Inventor

Junhyeok Ahn

Brief explanation

The patent application describes a semiconductor device with various layers and structures.

• The device includes a first contact structure, a first conductive wiring, a first etch-stop layer, and an interlayer insulating layer.
• There is also a second contact structure, a second conductive wiring, and a barrier layer.
• The barrier layer has a first barrier portion, a second etch-stop layer, and an air gap.
• The device is designed to improve the performance and functionality of semiconductor devices.

Abstract

A semiconductor device includes a first contact structure connected to the lower structure, a first conductive wiring connected to the first contact structure, a first etch-stop layer and an interlayer insulating layer sequentially provided on the first conductive wiring, a second contact structure passing through the first etch-stop layer, provided in the interlayer insulating layer, and connected to the first conductive wiring, a second conductive wiring provided on the second contact structure and provided in the interlayer insulating layer, a barrier layer including a first barrier portion on a bottom surface of the second contact structure, a second etch-stop layer provided on a top surface of the second conductive wiring and a top surface of the interlayer insulating layer, and an air gap between the barrier layer and the extension portion.

SEMICONDUCTOR PACKAGE (18098972)

Main Inventor

SEONGHO SHIN

Brief explanation

The patent application describes a semiconductor package design.

• The package includes a solder ball, a printed circuit board, a bump, and a semiconductor chip.
• The printed circuit board has multiple layers, including a base substrate and a low-k dielectric layer that goes through the base substrate.
• There is a connection conductive structure on the printed circuit board that is electrically connected to the bump and surrounded by the low-k dielectric layer.
• A lower conductive structure is also present on the printed circuit board, which is electrically connected to the solder ball and the connection conductive structure.
• The lower conductive structure's top surface is in contact with the bottom surface of the low-k dielectric layer.
• The design aims to provide improved electrical connections and protection for the semiconductor chip.

Abstract

Disclosed is a semiconductor package comprising a solder ball, a printed circuit board on the solder ball, a bump on the printed circuit board, and a semiconductor chip on the bump. The printed circuit board includes a base substrate, a low-k dielectric layer that penetrates the base substrate, a connection conductive structure electrically connected to the bump and surrounded by the low-k dielectric layer, and a lower conductive structure electrically connected to the solder ball and the connection conductive structure. A top surface of the lower conductive structure is in contact with a first bottom surface of the low-k dielectric layer.

SEMICONDUCTOR PACKAGE (18140985)

Main Inventor

JIWON SHIN

Brief explanation

The patent application describes a semiconductor package that includes two sub-semiconductor devices stacked on top of each other, with a heat sink covering the top device.

• The package consists of a first sub-semiconductor device with a substrate and a chip, an interposer, and a second sub-semiconductor device.
• The interposer has a dielectric layer, a thermal conductive layer, a first thermal conductive pad, and thermal conductive vias.
• The thermal conductive layer is in contact with the bottom surface of the dielectric layer and is connected to the top surface of the first semiconductor chip.
• The second sub-semiconductor device is placed on the dielectric layer without overlapping the first thermal conductive pad.
• The heat sink covers the second sub-semiconductor device and is connected to the first thermal conductive pad.

Abstract

A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

NON-VOLATILE MEMORY DEVICE (17983469)

Main Inventor

Changhun KIM

Brief explanation

The patent application describes a non-volatile memory device with a stacked chip design.

• The device includes a first chip with a substrate and a circuit element.
• A second chip is stacked on top of the first chip and has a substrate with two cell regions.
• Gate electrodes are stacked on one of the cell regions between the second substrate and the first chip.
• An upper insulating layer covers the second substrate and has dummy pads and input/output pads.
• A cover layer on top of the upper insulating layer exposes the input/output pads to the outside.
• Dummy contact plugs on one side of the second substrate penetrate the upper insulating layer and connect the dummy pads and the circuit element.

Abstract

A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.

SEMICONDUCTOR PACKAGE (18120866)

Main Inventor

Junyoung KO

Brief explanation

The patent application describes a semiconductor package design.

• The package includes a substrate with two surfaces, a redistribution layer on one surface, and a dielectric layer between the substrate and the redistribution layer.
• A semiconductor chip is placed between the substrate and the redistribution layer and is electrically connected to the redistribution layer.
• A connection structure is present between the substrate and the redistribution layer, which is also electrically connected to both surfaces.
• The dielectric layer covers the semiconductor chip and the connection structure and extends between the semiconductor chip and the substrate surface.

Abstract

A semiconductor package is provided. The semiconductor package includes a substrate including first and second surfaces opposite to each other, a redistribution layer on the first surface and having third and fourth surfaces opposite to each other wherein the third surface of the redistribution layer faces the first surface, a semiconductor chip between the substrate and the redistribution layer, the semiconductor chip spaced apart from the first surface and electrically connected to the third surface, a connection structure between the substrate and the redistribution layer and horizontally spaced apart from the semiconductor chip wherein the connection structure is electrically connected to the first surface and the third surface, and a dielectric layer between the substrate and the redistribution layer. The dielectric layer covers the semiconductor chip and the connection structure and extends between the semiconductor chip and the first surface.

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME (18057305)

Main Inventor

Yunsun Jang

Brief explanation

The patent application describes three-dimensional semiconductor memory devices and electronic systems.

• The memory device includes a first substrate with a cell array region and a contact region.
• A peripheral circuit structure is present on the first substrate.
• A cell array structure is stacked on the peripheral circuit structure, consisting of interlayer dielectric layers and gate electrodes.
• A dielectric layer is placed on top of the stack structure.
• A second substrate is placed on the stack structure.
• A mold structure made of dielectric material penetrates the stack structure.
• The mold structure contains a first through structure and a second through structure, which are spaced apart from each other.

Abstract

Disclosed are three-dimensional semiconductor memory devices and electronic systems. The three-dimensional semiconductor memory device includes a first substrate that includes a cell array region and a contact region, a peripheral circuit structure on the first substrate, a cell array structure on the peripheral circuit structure wherein the cell array structure includes interlayer dielectric layers and gate electrodes that are alternately stacked, a dielectric layer on the stack structure, and a second substrate on the stack structure, a mold structure that penetrates the stack structure and includes a dielectric material, and a first through structure and a second through structure that penetrate the mold structure and are spaced apart from each other.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18143983)

Main Inventor

Changbo LEE

Brief explanation

The patent application describes semiconductor devices and methods of fabricating them.

• The method involves using a carrier substrate with a conductive layer.
• A semiconductor die is placed on the carrier substrate.
• An insulating layer is formed to cover the semiconductor die.
• A via hole is created in the insulating layer to expose the conductive layer of the carrier substrate.
• A plating process is performed using the conductive layer as a seed to fill the via hole.
• A first redistribution layer is formed on the first surface of the semiconductor die and the insulating layer.
• The carrier substrate is removed.
• A second redistribution layer is formed on the second surface of the semiconductor die and the insulating layer.

Abstract

Disclosed are semiconductor devices and methods of fabricating the same. The method comprises providing a carrier substrate that includes a conductive layer, placing a semiconductor die on the carrier substrate, forming an insulating layer to cover the semiconductor die on the carrier substrate, forming a via hole to penetrate the insulating layer at a side of the semiconductor die and to expose the conductive layer of the carrier substrate, performing a plating process in which the conductive layer of the carrier substrate is used as a seed to form a via filling the via hole, forming a first redistribution layer on a first surface of the semiconductor die and the insulating layer, removing the carrier substrate, and forming a second redistribution layer on a second surface of the semiconductor die and the insulating layer, the first surface and the second surface being located opposite each other.

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME (18303360)

Main Inventor

Won Hee HWANG

Brief explanation

The abstract describes a semiconductor package design that includes multiple layers of semiconductor chips stacked on top of each other with a spacer in between. The design also includes trenches filled with a mold layer.

• The semiconductor package includes multiple layers of semiconductor chips.
• The chips are spaced apart from each other in a specific direction.
• There is a spacer between the topmost and bottommost chips.
• The design includes trenches that extend in the same direction as the chip spacing.
• The trenches are filled with a mold layer.

Abstract

A semiconductor package is provided. The semiconductor package includes a substrate; a plurality of first semiconductor chips on the substrate and spaced apart from each other in a first direction; a plurality of second semiconductor chips on the plurality of first semiconductor chips; a spacer between an uppermost one of the plurality of first semiconductor chips and a lowermost one of the plurality of second semiconductor chips, a plurality of trenches extending in the first direction; and a mold layer within the plurality of trenches.

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME (18448284)

Main Inventor

EUNKYUL OH

Brief explanation

- The patent application is about a semiconductor package and a method for manufacturing it.

- The method involves stacking semiconductor chips using a thermo-compression bonding (TCB) method to minimize defects and increase reliability. - The semiconductor package includes an interface chip with a first test pad, a bump pad inside the first test pad, and a first through silicon via (TSV) between the first test pad and the bump pad. - There is at least one memory chip stacked on the interface chip, which includes a second test pad, a dummy pad inside the second test pad, and a second TSV between the second test pad and the dummy pad. - An adhesive layer is provided between the interface chip and the memory chip. - The first test pad and the second test pad do not have any bumps on them.

Abstract

The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.

SEMICONDUCTOR PACKAGE (18069318)

Main Inventor

YeongBeom Ko

Brief explanation

The abstract describes a semiconductor package that includes a semiconductor module on a substrate.

• The semiconductor module consists of a first semiconductor chip with two surfaces, a second semiconductor chip, conductive pillars, and a redistribution substrate.
• The conductive pillars are connected to the first surface of the first semiconductor chip and the third surface of the redistribution substrate.
• The redistribution substrate is also connected to the second semiconductor chip.
• The fourth surface of the redistribution substrate is connected to the substrate of the semiconductor package.
• This design allows for efficient electrical connections between the semiconductor chips and the substrate.

Abstract

A semiconductor package includes at least one semiconductor module on a substrate. The semiconductor module includes a first semiconductor chip having a first surface and a second surface opposite to the first surface, a second semiconductor chip on the first surface, a plurality of conductive pillars on the first surface, and a redistribution substrate on the second semiconductor chip and the plurality of conductive pillars. The redistribution substrate has a third surface and a fourth surface opposite to the third surface. The third surface of the redistribution substrate faces the first surface of the first semiconductor chip, the plurality of conductive pillars are electrically connected to the first surface of the first semiconductor chip and the third surface of the redistribution substrate, and the fourth surface of the redistribution substrate is electrically connected to the substrate of the semiconductor package.

SEMICONDUCTOR PACKAGE AND STACKED PACKAGE MODULE INCLUDING THE SAME (18447535)

Main Inventor

Daeho LEE

Brief explanation

The patent application describes a semiconductor package design that includes multiple layers and ball pads for improved functionality and performance.

• The semiconductor package includes a lower redistribution layer with multiple lower ball pads grouped together.
• A semiconductor chip is placed on top of the lower redistribution layer.
• An expanded layer surrounds the semiconductor chip on the lower redistribution layer.
• An upper redistribution layer is placed on top of the semiconductor chip and expanded layer.
• The upper redistribution layer has multiple upper ball pads grouped together.
• The number of upper ball pad groups is the same as the number of lower ball pad groups.
• Some of the upper ball pads in each group may be dummy ball pads, which are not connected to any external components.

Abstract

A semiconductor package includes a lower redistribution layer having a plurality of lower ball pads forming a plurality of lower ball pad groups, a semiconductor chip on the lower redistribution layer, an expanded layer surrounding the semiconductor chip on the lower redistribution layer, and an upper redistribution layer on the semiconductor chip and the expanded layer and having a plurality of upper ball pads forming a plurality of upper ball pad groups. The number of the plurality of upper ball pad groups may be the same as the number of the of the plurality lower ball pad groups. Each of the upper ball pads in one of the plurality of upper ball pad groups, from among the plurality of upper ball pads, may be a dummy ball pad.

DISPLAY MODULE AND DISPLAY APPARATUS HAVING THE SAME (18208034)

Main Inventor

Jaeseok Kim

Brief explanation

- The patent application describes a display module that uses an inorganic light emitting device.

- The display module includes a substrate and a thin film transistor (TFT) layer on the substrate. - There are also connection pads on the TFT layer and an anisotropic conductive layer on top of it. - The anisotropic conductive layer consists of an adhesive layer with conductive balls distributed inside it. - The inorganic light emitting element is bonded to the anisotropic conductive layer and has electrodes corresponding to the connection pads. - A conductive ball control layer is present around the connection pads to prevent the conductive balls from moving in a direction perpendicular to the bonding direction during the bonding process.

Abstract

In some embodiments, a display module for implementing an image using an inorganic light emitting device includes a substrate, a thin film transistor (TFT) layer provided on the substrate, a plurality of connection pads provided on the TFT layer, an anisotropic conductive layer provided on the TFT layer, an inorganic light emitting element bonded to the anisotropic conductive layer, and a conductive ball control layer provided in a surrounding area of the plurality of connection pads. The anisotropic conductive layer includes an adhesive layer and a plurality of conductive balls distributed inside the adhesive layer. The inorganic light emitting element includes a plurality of electrodes corresponding to the plurality of connection pads. The conductive ball control layer is configured to restrict the plurality of conductive balls from moving in a direction perpendicular to a bonding direction while the inorganic light emitting element is being bonded to the anisotropic conductive layer.

SEMICONDUCTOR DEVICE (18094452)

Main Inventor

Su Young BAE

Brief explanation

The patent application describes a semiconductor device with a specific structure and arrangement of layers within a gate trench. 

• The device includes a substrate and an active pattern on the substrate, extending in one direction.
• A gate spacer is placed along the sidewalls of the gate trench on the active pattern, extending in a different direction.
• A first gate insulating layer is positioned along the sidewall and bottom surface of the gate trench.
• A first conductive layer is placed on the first gate insulating layer inside the gate trench.
• A second gate insulating layer, made of a different material than the first gate insulating layer, is placed on top of the first conductive layer.
• A second conductive layer is then placed on the second gate insulating layer inside the gate trench.
• Finally, a third conductive layer is added to fill the remaining inner space of the gate trench.

Abstract

A semiconductor device includes a substrate, an active pattern disposed on the substrate and extending in a first horizontal direction, a gate spacer disposed along each of sidewalls of a gate trench on the active pattern and extending in a second horizontal direction different from the first horizontal direction, a first gate insulating layer disposed along a sidewall and a bottom surface of the gate trench, a first conductive layer disposed on the first gate insulating layer inside the gate trench, a second gate insulating layer disposed on the first conductive layer inside the gate trench, and including a material different from a material of the first gate insulating layer, a second conductive layer disposed on the second gate insulating layer inside the gate trench, and a third conductive layer disposed on the second conductive layer so as to fill a remaining inner space of the gate trench.

DISPLAY MODULE, DISPLAY APPARATUS AND METHOD FOR MANUFACTURING SAME (18227162)

Main Inventor

Youngki JUNG

Brief explanation

The patent application describes a display module with a two-dimensional arrangement of pixels and a display panel with a transparent substrate, pixel circuit layer, and power electrode layers. The display panel also includes inorganic light emitting elements.

• The display module includes multiple pixels, each containing two or more inorganic light emitting elements.
• The display panel has transparent regions corresponding to the position of an image sensor.
• The transparent regions allow external light to reach the image sensor.
• The image sensor is located on the rear of the display panel.

Abstract

A display module includes: a plurality of pixels arranged in two dimensions; a display panel including: a back plate including: a transparent substrate; a pixel circuit layer; and a plurality of power electrode layers provided on the transparent substrate; and a plurality of inorganic light emitting elements provided on the back plate; and an image sensor provided on the rear of the display panel, wherein each of the plurality of pixels includes two or more inorganic light emitting elements among the plurality of inorganic light emitting elements, the display panel includes a plurality of transparent regions in a region corresponding to a position of the image sensor, and each transparent region of the plurality of transparent regions is configured to allow external light to be incident on the image sensor.

SEMICONDUCTOR DEVICE (18095561)

Main Inventor

Intak JEON

Brief explanation

The patent application describes a semiconductor device with specific layers and materials.

• The device includes a substrate, lower electrodes, a support layer, an upper electrode, a dielectric layer, and a blocking layer.
• The lower electrodes are placed on the substrate, and the support layer is in contact with them, extending parallel to the substrate's upper surface.
• The upper electrode is positioned on top of the lower electrodes and the support layer.
• A dielectric layer is present between the lower electrodes and the upper electrode, as well as between the support layer and the upper electrode.
• A blocking layer is placed between the support layer and the dielectric layer, and it has a material with a higher bandgap energy than the support layer's material.
• The dielectric layer is in contact with the lower electrodes and is separated from the support layer by the blocking layer.

Abstract

A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate, at least one support layer in contact with the plurality of lower electrodes and extending in a direction, parallel to an upper surface of the substrate, an upper electrode disposed on the plurality of lower electrodes and the at least one support layer, a dielectric layer between the plurality of lower electrodes and the upper electrode and between the at least one support layer and the upper electrode, and a blocking layer disposed between the at least one support layer and the dielectric layer, and including a material having a bandgap energy greater than a bandgap energy of a material of the at least one support layer. The dielectric layer is in contact with the plurality of lower electrodes and is spaced apart from the at least one support layer by the blocking layer.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18100233)

Main Inventor

Ki Hwan KIM

Brief explanation

The patent application describes a semiconductor device with specific features to improve its performance. Here are the key points:

• The device includes a substrate with an active pattern, a source/drain pattern, a gate electrode, and a gate spacer.
• The source/drain pattern consists of two semiconductor layers - a first layer on the active pattern and a second layer on top of the first layer.
• The first semiconductor layer has inner sidewalls, and the distance between these sidewalls decreases as two specific portions of the layer get closer to the gate spacer.

In summary, the patent application introduces a semiconductor device design that optimizes the distance between inner sidewalls of a specific semiconductor layer, resulting in improved performance.

Abstract

A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.

SEMICONDUCTOR DEVICE (18117262)

Main Inventor

Ki Hwan KIM

Brief explanation

The patent application describes a semiconductor device with a unique structure for improved performance. 

• The device includes an active pattern with a lower pattern and multiple sheet patterns spaced apart from the lower pattern in one direction.
• It also has gate structures with gate electrodes and gate insulating films, arranged in a second direction and spaced apart from each other.
• Source/drain recesses are defined between adjacent gate structures, and a source/drain pattern fills these recesses.
• The source/drain pattern consists of a first semiconductor liner, which extends along the sidewalls and bottom surface of the recesses.
• On top of the first semiconductor liner, there are second semiconductor liners that are doped with carbon and also extend along the sidewalls and bottom surface of the recesses.
• Finally, a filling semiconductor film is on top of the second semiconductor liners and fills the source/drain recess.
• The first semiconductor liners are in contact with the lower pattern and sheet patterns, and they include regions without carbon doping.

Abstract

A semiconductor device comprises an active pattern including a lower pattern and a plurality of sheet patterns that are spaced apart from the lower pattern in a first direction, a plurality of gate structures disposed on the lower pattern to be spaced apart from each other in a second direction, each of the gate structures including a gate electrode and gate insulating films, source/drain recesses defined between adjacent gate structures and a source/drain pattern filling the source/drain recesses. Each source/drain pattern may include a first semiconductor liner, which extend along sidewalls and a bottom surface of the source/drain recesses, second semiconductor liners, which are on the first semiconductor liners and extend along the sidewalls and the bottom surface of the source/drain recesses, and a filling semiconductor film, which is on the second semiconductor liners and fills the source/drain recess. The second semiconductor liners may be doped with carbon, and the first semiconductor liners may be in contact with the lower pattern and the sheet patterns, while the first semiconductor liners may include carbon-undoped regions.

INTEGRATED CIRCUIT DEVICES (18155532)

Main Inventor

Juri LEE

Brief explanation

The patent application describes an integrated circuit (IC) device with a specific structure for the source/drain region. 

• The IC device has a fin-type active region on a substrate, a channel region, a gate line, and a source/drain region.
• The source/drain region is divided into a lower region and an upper region.
• The lower region contains a specific silicon isotope (Si, Si, or Si), while the upper region has a higher content of a Si element compared to the lower region.

Abstract

An integrated circuit (IC) device includes a fin-type active region extending long in a first lateral direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region, and a source/drain region adjacent to the gate line on the fin-type active region, the source/drain region. The source/drain region includes a lower source/drain region and an upper source/drain region. The lower source/drain region includes at least one silicon isotope selected from silicon isotopes of Si, Si, and Si, and the upper source/drain region includes a Si element at a content higher than a content of the Si element in the lower source/drain region.

SEMICONDUCTOR DEVICES (18189538)

Main Inventor

Hyohoon Byeon

Brief explanation

The patent application describes a semiconductor device with a unique structure and composition.

• The device includes a substrate with an active region and a gate structure intersecting the active region.
• Multiple channel layers are arranged on the active region and surrounded by the gate structure.
• Source/drain regions are located on opposite sides of the gate structure and connected to the channel layers.
• Each channel layer consists of three semiconductor layers stacked on top of each other.
• The first and third layers are made of silicon (Si), while the second layer is made of silicon-germanium (SiGe).
• The side surfaces of the semiconductor layers are in contact with the gate structure.

Abstract

A semiconductor device includes a substrate including an active region extending in a first direction, a gate structure intersecting the active region on the substrate and extending in a second direction, a plurality of channel layers spaced apart from each other in a third direction, perpendicular to an upper surface of the substrate, on the active region and surrounded by the gate structure, and source/drain regions in recess regions of the active region, on opposite sides adjacent to the gate structure and electrically connected to the plurality of channel layers. Each of the plurality of channel layers includes first to third semiconductor layers sequentially stacked in the third direction, the first and third semiconductor layers include silicon (Si), and the second semiconductor layer includes silicon-germanium (SiGe). Side surfaces of the first to third semiconductor layers in the second direction are in contact with the gate structure.

SEMICONDUCTOR DEVICES (18449734)

Main Inventor

MYUNG GIL KANG

Brief explanation

The patent application describes a semiconductor device with a unique structure for improved performance. 

• The device includes a first active pattern consisting of a lower pattern and a sheet pattern, both arranged in a specific direction.
• A gate electrode is positioned on the lower pattern, surrounding the sheet pattern, and extending in a different direction.
• The lower pattern has two opposite sidewalls, each extending in the same direction as the active pattern.
• The gate electrode overlaps one sidewall of the lower pattern by a certain depth, and the other sidewall by a different depth.
• The depth of overlap on each sidewall is not the same, providing a distinct configuration for the device.

Abstract

Semiconductor devices include a first active pattern including a first lower pattern extending in a first direction and a first sheet pattern spaced apart from the first lower pattern; and a first gate electrode on the first lower pattern, the first gate electrode extending in a second direction and surrounding the first sheet pattern, wherein the first lower pattern includes a first sidewall and a second sidewall opposite to each other, each of the first sidewall of the first lower pattern and the second sidewall of the first lower pattern extends in the first direction, the first gate electrode overlaps the first sidewall of the first lower pattern in the second direction by a first depth, the first gate electrode overlaps the second sidewall of the first lower pattern in the second direction by a second depth, and the first depth is different from the second depth.

SEMICONDUCTOR DEVICES (18106631)

Main Inventor

Kijoon KIM

Brief explanation

The patent application describes a semiconductor device with channel structures arranged vertically.

• The device includes gate insulation patterns that make contact with the channel structures.
• A gate electrode surrounds the channel structures and their sidewalls.
• Source and drain layers are located on the sides of the gate electrode.
• The channel structures consist of two layers of 2D materials stacked vertically.
• The first layer is made of a semiconducting TMD (transition metal dichalcogenide) with a first transition metal and chalcogen elements bonded to it.
• The second layer includes a second transition metal and a second chalcogen element bonded to it.
• The second transition metal in the second layer is covalently or ionically bonded to an element in the upper gate insulation pattern.

Abstract

A semiconductor device includes channel structures spaced apart in a vertical direction; lower/upper first gate insulation patterns contacting lower/upper surfaces of the channel structures; a gate electrode surrounding lower/upper surfaces and a sidewall of the channel structures; and source/drain layers at sides of the gate electrode, wherein the channel structures include first/second 2D material layers stacked in the vertical direction, the first 2D material layer includes a semiconducting TMD including a first transition metal and first chalcogen elements that are bonded at lower/upper sides of the first transition metal, the second 2D material layer includes a second transition metal and a second chalcogen element, the second chalcogen element being bonded at a lower side of the second transition metal, and the second transition metal included in the second 2D material layer is covalently or ionically bonded with an element of the upper first gate insulation pattern.

SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME (18151021)

Main Inventor

Ki Heun Lee

Brief explanation

- The patent application describes a semiconductor device that includes a ferroelectric field effect transistor (FeFET).

- The device is fabricated on a substrate and includes a gate electrode film made of a metal element. - A gate insulating film, made of a ferroelectric material, is positioned between the substrate and the gate electrode film. - A buffer oxide film, made of an oxide of a semiconductor material, is located between the gate insulating film and the gate electrode film. - The buffer oxide film is in contact with the gate insulating film. - The invention provides a method for fabricating this semiconductor device.

Abstract

A semiconductor device including a ferroelectric field effect transistor (FeFET) and a method for fabricating the same are provided. The semiconductor device includes a substrate, a gate electrode film including a metal element, on the substrate, a gate insulating film including a ferroelectric material between the substrate and the gate electrode film, and a buffer oxide film including an oxide of a semiconductor material between the gate insulating film and the gate electrode film, the buffer oxide film being in contact with the gate insulating film.

ACTIVE PATTERN STRUCTURE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME (18360457)

Main Inventor

Sangmoon LEE

Brief explanation

The patent application describes an active pattern structure with specific components and their arrangement.

• The structure includes a lower active pattern that sticks out from the substrate's upper surface in a vertical direction.
• A buffer structure is present on the lower active pattern, potentially containing aluminum silicon oxide.
• An upper active pattern is placed on top of the buffer structure.

Abstract

An active pattern structure includes a lower active pattern protruding from an upper surface of a substrate in a vertical direction substantially perpendicular to an upper surface of the substrate, a buffer structure on the lower active pattern, at least a portion of which may include aluminum silicon oxide, and an upper active pattern on the buffer structure.

DISPLAY MODULE INCLUDING MICRO LIGHT EMITTING DIODES (18205312)

Main Inventor

Yoonsuk LEE

Brief explanation

The patent application describes a display assembly that includes multiple light emitting diodes (LEDs) and electrodes on the LEDs. These LEDs are fixed to a substrate using an adhesive layer. The adhesive layer consists of a non-conductive polymer resin, a flux agent mixed with the resin, and conductive particles dispersed in the resin. These conductive particles connect the electrodes of the LEDs to electrode pads on the substrate.

• The display assembly includes multiple LEDs and electrodes on the LEDs.
• The LEDs are fixed to a substrate using an adhesive layer.
• The adhesive layer consists of a non-conductive polymer resin, a flux agent, and conductive particles.
• The conductive particles connect the electrodes of the LEDs to electrode pads on the substrate.

Abstract

Provided is a display assembly including a plurality of light emitting diodes, a plurality of electrodes provided on the plurality of light emitting diodes, a substrate, a plurality of electrode pads provided on the substrate, the plurality of electrode pads being connected to the electrodes provided on the plurality of light emitting diodes, and an adhesive layer fixing the plurality of light emitting diodes to the substrate, wherein the adhesive layer includes a non-conductive polymer resin, a flux agent mixed with the non-conductive polymer resin, and a plurality of conductive particles dispersed in the non-conductive polymer resin and connecting the electrodes of the light emitting diodes and the plurality of electrode pads.

LITHIUM SOLID ELECTROLYTE AND METHOD OF MANUFACTURE THEREOF (18361290)

Main Inventor

Yuntong Zhu

Brief explanation

The patent application describes a method of manufacturing a lithium solid electrolyte. 

• The method involves providing a composition that includes a lithium precursor, a lanthanum precursor, and a zirconium precursor.
• The composition is then disposed on a substrate that has a temperature ranging from 270°C to 500°C, resulting in the formation of a film.
• The film is subsequently heat-treated at a temperature between 300°C and less than 750°C for a duration of 1 hour to 100 hours.
• This heat treatment process allows for the production of the lithium solid electrolyte.

Abstract

A method of manufacturing a lithium solid electrolyte, the method including: providing a composition including a lithium precursor, a lanthanum precursor, and a zirconium precursor; disposing the composition on a substrate having a temperature of 270° C. to 500° C. to form a film; and heat-treating the film at 300° C. to less than 750° C. for 1 hour to 100 hours to manufacture the lithium solid electrolyte.

ELECTRONIC DEVICE COMPRISING ANTENNA (18138703)

Main Inventor

Taegyeong Han

Brief explanation

The patent application describes an electronic device with two housings, one of which has a protrusion designed to fit on an ear. 

• The device includes a printed circuit board, a wireless communication circuit, and an antenna carrier located inside the two housings.
• The antenna carrier has a first surface, a second surface, and through holes.
• A conductive pattern is formed on the first and second surfaces and is connected to the wireless communication circuit.
• The antenna carrier also has a groove structure on its second surface, which is in contact with a second through hole.
• The wireless communication circuit uses the conductive pattern to transmit and receive wireless signals by providing power to it.

Abstract

An electronic device includes a first housing connected to a second housing having a protrusion configured to be seated on an ear. The electronic device also includes a printed circuit board, a wireless communication circuit, an antenna carrier disposed in internal space defined by the first housing and the second housing. The electronic device also includes a conductive pattern formed over the first surface and the second surface through a first through hole and electrically connected to the wireless communication circuit. The antenna carrier includes a first surface, a second surface opposite to the first surface, and through holes passing through the antenna carrier. The antenna carrier also includes a groove structure including a portion in contact with a second through hole and formed on the second surface of the antenna carrier. The wireless communication circuit transmits and/or receives a wireless signal by providing power to the conductive pattern.

ANTENNA STRUCTURE AND ELECTRONIC DEVICE COMPRISING SAME (18446906)

Main Inventor

Youngsub KIM

Brief explanation

The abstract describes a communication system that supports a higher data transmission rate than 4G systems.

• The system is specifically designed for 5G or pre-5G communication.
• It includes an antenna structure with a first radiator and a first printed circuit board (PCB).
• There are also multiple second radiators and a second PCB.
• A frame structure is arranged to create an air layer between the first and second PCBs.
• The second radiators can include a first metal patch corresponding to the first radiator.
• There are also multiple second metal patches that are separated from the first metal patch and fed by coupling.

Abstract

The disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a data transmission rate higher than that of a 4th generation (4G) communication system such as long term evolution (LTE). An antenna structure of a wireless communication system is provided. The antenna structure includes a first radiator, a first printed circuit board (PCB) in which the first radiator is arranged, a plurality of second radiators, a second PCB in which the plurality of second radiators are arranged, and a frame structure, wherein the frame structure is arranged such that an air layer is formed between the first PCB and the second PCB, and the plurality of second radiators can include a first metal patch arranged in a region corresponding to the first radiator, and a plurality of second metal patches arranged to be separated from the first metal patch so as to be fed by coupling.

CONNECTOR AND ELECTRONIC DEVICE INCLUDING THE SAME (18339578)

Main Inventor

Junhwa CHOI

Brief explanation

The abstract describes an example electronic device with a connector and a printed circuit board connected to the connector.

• The connector includes a mid plate with a first and second surface.
• There are multiple terminals and an insulating structure that supports some of the terminals.
• One of the terminals is a ground terminal that is spaced apart from the mid plate in a certain direction.
• The ground terminal extends in the length direction of the connector and is in contact with both the mid plate and the printed circuit board.

Abstract

An example electronic device may include a connector; and a printed circuit board electrically connected to the connector, wherein the connector may include: a mid plate that includes a first surface and a second surface opposite to the first surface; a plurality of terminals; and an insulating structure in which at least a part of the mid plate is disposed and supporting at least some of the plurality of terminals, wherein the plurality of terminals may include a ground terminal that is disposed to be spaced apart at least in part in a first direction or in a second direction opposite to the first direction with respect to the mid plate, is extended in a length direction of the connector, and is in contact with the mid plate at one end thereof and is in contact with the printed circuit board at the other end thereof.

ELECTRONIC DEVICE AND CONTROL METHOD THEREFOR (18448484)

Main Inventor

Jaesung LEE

Brief explanation

The patent application describes an electronic device with a battery, a sensor module, a power reception unit, a power management module, and a processor.

• The sensor module measures the temperature of a specific area near the battery.
• The power reception unit wirelessly receives power from a charging device.
• The power management module controls the supply of power to the battery and the internal system of the device.
• The processor is connected to the sensor module and the power management module.
• When the device is wirelessly charging, the processor sends a command to the power management module to stop supplying power to the battery once it is fully charged.
• The power is then redirected to the internal system of the device.
• The sensor module is used to measure a second temperature.
• The processor controls the power supplied to the internal system based on the second temperature.

Abstract

An electronic device is provided. The electronic device includes a battery, a sensor module for acquiring a first temperature, which is the temperature of a first portion adjacent to the battery, a power reception unit for wirelessly receiving power from a charging device, a power management module for supplying power to the battery and an internal system of the electronic device, and a processor electrically connected to the sensor module and the power management module, wherein, while the electronic device wirelessly receives power from the charging device, the processor is configured to transmit a first command to the power management module so the power management module cut offs the supply of the power to the battery and supplies the power to the internal system in response to the battery being fully charged, use the sensor module to acquire a second temperature, and control the power, supplied to the internal system.

WIRELESS CHARGING OF AN ELECTRONIC DEVICE (18320645)

Main Inventor

Youso CHEON

Brief explanation

The abstract describes a method for wirelessly charging an electronic device.

• The method involves a first electronic device entering a wireless charging mode when it detects that a second electronic device is accessing it.
• The first electronic device sets a power transmission duty ratio at a certain level and wirelessly supplies power to the second electronic device based on this ratio.
• The first electronic device continuously monitors the current value used to provide power to the second electronic device.
• Based on the monitored current value, the first electronic device adjusts the power transmission duty ratio accordingly.

Abstract

A method for wirelessly charging an electronic device includes entering, by a first electronic device a wireless charging mode upon determining that a second electronic device is accessing the first electronic device; the first electronic device setting a power transmission duty ratio of the first electronic device at a first level; the first electronic device wirelessly supplying power to the second electronic device at the power transmission duty ratio; the first electronic device monitoring a current value of the first electric device used to provide the power to the second electronic device; and the first electronic device controlling the power transmission duty ratio according to the monitored current value.

SWITCHING MODE POWER SUPPLY AND CONTROLLING METHOD THEREOF (18206428)

Main Inventor

Youngho CHOI

Brief explanation

The patent application describes a switching mode power supply that converts input alternating current (AC) voltage into a direct current (DC) voltage.

• The power input unit receives the input AC voltage.
• The rectification unit converts the input AC voltage into a rectified form.
• The condenser smooths the rectified voltage.
• The current detection unit detects any surge current flowing in the condenser.
• The converter, which includes switching elements, generates the DC voltage based on the voltage across the condenser and the on/off duty ratios of the switching elements.
• The switching elements are turned off when the current detection unit detects a surge current.

Abstract

A switching mode power supply including: a power input unit configured to receive an input alternating current (AC) voltage; a rectification unit configured to rectify the input AC voltage; a condenser configured to smooth the rectified input AC voltage; a current detection unit configured to detect a surge current flowing in the condenser; and a converter including switching elements, the converter being outputting a direct current (DC) voltage based on a voltage applied to first and second ends of the condenser and on/off duty ratios of the switching elements. The switching elements are configured to be turned off based on the surge current being detected by the current detection unit.

CLOCK GENERATOR AND ELECTRONIC DEVICE INCLUDING THE SAME (18154966)

Main Inventor

Hyunseok NAM

Brief explanation

The patent application describes a clock generating device that produces a stable clock signal.

• The device has a first voltage output circuit that generates a voltage corresponding to the power supply voltage.
• A clock output circuit generates a preliminary clock signal and a final clock signal based on the difference between the first voltage and a negative feedback voltage.
• A negative feedback voltage generating circuit generates the negative feedback voltage from a reference value corresponding to the frequency of the final clock signal.
• The negative feedback voltage is filtered to a uniform voltage level.
• A second voltage output circuit outputs a second voltage to the negative feedback voltage generating circuit.
• The second voltage has lower sensitivity to fluctuations in the power supply voltage compared to the first voltage.

Abstract

A clock generating device includes a first voltage output circuit configured to output a first voltage corresponding to a power supply voltage in response to a preliminary clock signal, a clock output circuit configured to generate the preliminary clock signal and a final clock signal at a period corresponding to a difference between the first voltage and a negative feedback voltage, a negative feedback voltage generating circuited configured to generate the negative feedback voltage from a reference value corresponding to a frequency of the final clock signal and a second voltage and filtered to a uniform voltage level, and a second voltage output circuit configured to output the second voltage to the negative feedback voltage generating unit, the second voltage having lower sensitivity of fluctuations in the power supply voltage than the first voltage.

DELAY CONTROL CIRCUIT AND A MEMORY MODULE INCLUDING THE SAME (18101653)

Main Inventor

Bumsoo LEE

Brief explanation

The patent application describes a delay control circuit that is used to delay a signal by a specific amount of time. 

• The delay control circuit includes a delay cell, which consists of bias inverters, first RC circuits, and second RC circuits.
• The delay cell activates a certain number of first RC circuits based on a step code, and then delays the signal by a specific amount of time determined by the number of activated first RC circuits.
• The delayed signal is then outputted.

Additionally, the delay control circuit includes a ZQ calibrator, which consists of pull-up and pull-down circuits.

• The ZQ calibrator adjusts the number of activated pull-up and pull-down circuits based on a calibration code, and also inputs a pull-up and pull-down voltage to the bias inverters.

Furthermore, the delay control circuit includes a step adjuster, which consists of a first ring oscillator with test delay cells.

• The step adjuster determines the characteristics of the first and second RC circuits and activates a certain number of second RC circuits based on these characteristics and the operating frequency of the delay control circuit.

Abstract

A delay control circuit includes: a delay cell including a plurality of bias inverters, first RC circuits, and second RC circuits, the delay cell activates a number of first RC circuits in response to a step code, delays a signal by a delay time based on the number of the activated first RC circuits, and outputs the delayed signal; a ZQ calibrator including pull-up and pull-down circuits, the ZQ calibrator adjusts a number of activated pull-up and pull-down circuits, and inputs a pull-up and pull-down voltage, based on a calibration code to the bias inverters; and a step adjuster including a first ring oscillator including test delay cells, the step adjuster determining characteristics of the first and second RC circuits and activates a number of second RC circuits based on the characteristics and an operating frequency of the delay control circuit.

ELECTRONIC DEVICE AND METHOD FOR OBTAINING REVERSE SIGNAL AND FEEDBACK SIGNAL IN WIRELESS COMMUNICATION SYSTEM (18188106)

Main Inventor

Munwoo LEE

Brief explanation

The patent application describes an electronic device that includes various components such as a digital pre-distortion (DPD), a digital-to-analog converter (DAC), a power amplifier (PA), and more. 

• The device includes a feedback system that uses a first coupler to obtain a feedback signal from the output of the power amplifier.
• A circulator is used to obtain a reverse signal, which is a reflection of the output of the power amplifier.
• A transmission filter is included in the device, and a second coupler is used to obtain a filter-feedback signal from the output of the transmission filter.
• The device also includes an antenna for transmitting and receiving signals.
• An analog-to-digital converter (ADC) is used to convert a composite signal, which includes the feedback signal, filter-feedback signal, and reverse signal, into a digital composite signal.
• A separation circuit is included in the device to separate the digital composite signal into individual digital signals for the feedback signal, filter-feedback signal, and reverse signal.
• A pulse inter-modulation cancellation (PIMC) circuit is used to process the separated digital signals along with an input signal of the DPD, in order to obtain processed digital signals for the feedback signal, filter-feedback signal, and reverse signal.

Abstract

An electronic device is provided. The electronic device includes a digital pre-distortion (DPD), a digital-to-analog converter (DAC), a power amplifier (PA), a first coupler obtaining a feedback signal from an output of the power amplifier, a circulator obtaining a reverse signal in which the output of the power amplifier is reflected, a transmission filter, a second coupler obtaining a filter-feedback signal from an output of the transmission filter, an antenna, an analog-to-digital converter (ADC) converting a composite signal including the feedback signal, the filter-feedback signal, and the reverse signal into a digital composite signal, a separation circuit, and a pulse inter-modulation cancellation (PIMC) circuit in which the separation circuit, based on the digital composite signal and an input signal of the DPD, obtains a digital signal of the feedback signal, a digital signal of the filter-feedback signal, and a digital signal of the reverse signal.

MULTI-ANTENNA WIFI BASED BREATHING RATE ESTIMATION (18321614)

Main Inventor

Vishnu Vardhan Ratnam

Brief explanation

- The patent application describes a method for estimating and compensating for errors in amplitude and phase of Channel State Information (CSI) frames received from another electronic device.

- The method involves estimating the CSI from each received frame and identifying an impairment model that accounts for errors in amplitude and phase. - The errors in amplitude and phase of the CSI estimates are then compensated for using various techniques such as approximating missing CSI estimates, determining an AGC gain value, or computing errors in phase using a weighted least-squares solution. - The compensated CSI estimates are used to estimate the breathing rate of a subject based on different spatial dimensions. - The innovation aims to improve the accuracy of CSI estimation and compensate for errors, allowing for more reliable estimation of the subject's breathing rate.

Abstract

A method includes receiving CSI frames among P CSI frames transmitted from another electronic device. The method includes estimating a CSI from each of the received CSI frames as an available CSI estimate. The method includes identifying an impairment model accounting for inclusion of amplitude or phase errors of an estimated CSI corresponding to a p-th CSI frame among the P CSI frames. The method includes compensating, via the impairment model, for the errors in amplitude and phase of P CSI estimates. Compensating for the errors in amplitude and phase of the P CSI estimates can be based on: approximating a missing CSI estimate based on the available CSI estimates; determining an AGC gain value; or computing the errors in the phase based on a weighted least-squares solution. The method includes estimating a breathing rate of a subject based on different spatial dimensions of the P compensated CSI estimates.

METHOD AND APPARATUS FOR CHANNEL ENCODING AND DECODING IN COMMUNICATION OR BROADCASTING SYSTEM (18365668)

Main Inventor

Seho MYUNG

Brief explanation

- The patent application is for a communication system that supports higher data rates than current 4G systems.

- The system uses a channel encoding method to improve data transmission. - The method involves identifying the size of the input data, determining a block size, and using a low density parity check (LDPC) sequence for encoding. - LDPC encoding is performed based on the LDPC sequence and the block size. - The innovation aims to enhance the efficiency and speed of data transmission in communication and broadcasting systems.

Abstract

A pre-5th-generation (pre-5G) or 5G communication system for supporting higher data rates beyond a 4th-generation (4G) communication system, such as long term evolution (LTE) is provided. A channel encoding method in a communication or broadcasting system includes identifying an input bit size, determining a block size (Z), determining a low density parity check (LDPC) sequence to perform LDPC encoding, and performing the LDPC encoding based on the LDPC sequence and the block size.

METHODS, USER EQUIPMENT AND NON-TRANSITORY COMPUTER-READABLE MEDIA FOR AUTONOMOUS RESOURCE SELECTION (17946463)

Main Inventor

Jie DENG

Brief explanation

This patent application describes a method for autonomous resource selection by a user equipment (UE) in a network. Here are the key points:

• The method involves obtaining a sidelink resource set, which is a set of resources that can be used for communication between UEs.
• The network provides the UE with the number of current UEs participating in sidelink transmission in a serving cell and a first user identifier (ID).
• The UE assigns sequence numbers to different resource units within the sidelink resource set.
• Based on the number of current UEs and the first user ID, the UE selects a subset of resource units from the sidelink resource set.
• The subset of resource units is chosen based on specific sequence numbers assigned to them.
• The UE then uses these selected sidelink resources to transmit a communication signal.

Overall, this method allows a UE to autonomously select the appropriate sidelink resources for communication based on the number of UEs and its own user ID.

Abstract

A method for autonomous resource selection by a user equipment (UE). The method includes obtaining a sidelink resource set, a number of current UEs and a first user identifier (ID) from a network, the number of current UEs corresponding to UEs currently participating in sidelink transmission in a serving cell, assigning a plurality of sequence numbers to a plurality of resource units among the sidelink resource set, selecting a subset of the plurality of resource units as sidelink resources of the UE based on the number of current UEs and the first user ID, the subset of the plurality of resource units having particular sequence numbers from among the plurality of sequence numbers, and transmitting a communication signal using the sidelink resources of the UE.

ELECTRONIC DEVICE FOR REDUCING INTERFERENCE FROM REFERENCE SIGNAL, AND OPERATION METHOD THEREOF (18232089)

Main Inventor

Kyujae JANG

Brief explanation

The patent application describes an electronic device that can connect to both a legacy network and a 5G or 6G network simultaneously. However, transmitting reference signals to the 5G or 6G network can cause interference with signals received from the legacy network. The patent provides methods and devices to avoid this interference and ensure smooth communication between the two networks.

• Electronic device can connect to both a legacy network and a 5G or 6G network simultaneously
• Transmitting reference signals to the 5G or 6G network can interfere with signals received from the legacy network
• Methods and devices are provided to avoid interference and ensure smooth communication between the two networks

Abstract

An electronic device, which may be a dual-mode user equipment (UE), communicates with a first network and a second network. The first network may be a legacy network. The second network may be a 5G or 6G network. Transmission by the electronic device of reference signals to the second network may interfere reception at the electronic device of signals from the first network. Methods and devices are provided for avoiding interference when using the first and second networks.

ELECTRONIC DEVICE FOR ENCRYPTING BIOMETRIC DATA AND OPERATION METHOD OF ELECTRONIC DEVICE (18448972)

Main Inventor

Moonsoo CHANG

Brief explanation

- The patent application describes an electronic device that includes a biometric sensor for acquiring biometric data.

- The device has a processor with a general region and a trusted region, where a trusted application with a designated security level or higher is executed in the trusted region. - The device also includes a memory for storing encryption information related to registered biometric data. - There is a security processor physically separated from the main processor, which is responsible for encrypting the biometric data acquired by the sensor. - The main processor loads the encrypted biometric data onto the trusted region and extracts feature information for biometric authentication from the encrypted data. - The feature information is then compared with the encryption information stored in the memory. - Based on the result of the comparison, the device performs biometric authentication.

Abstract

An electronic device includes: a biometric sensor for acquiring biometric data; a processor including a general region, and a trusted region which is distinguished from the general region and in which a trusted application having a designated security level or higher is executed; a memory for storing encryption information (encryption data) related to registered biometric data; and a security processor which is physically separated from the processor, where the security processor is configured to encrypt the biometric data acquired by the sensor, and the processor is configured to: load the encrypted biometric data onto the trusted region, the biometric data being acquired from the security processor; extract feature information for biometric authentication from the encrypted biometric data; compare the feature information with the encryption information acquired from the memory; and perform the biometric authentication on the basis of a result of the comparison.

AI-AUGMENTED CHANNEL ESTIMATION (18183114)

Main Inventor

Yeqing Hu

Brief explanation

The patent application describes a method for estimating channel profiles in a communication system using machine learning and minimum mean square error (MMSE) techniques.

• The method determines estimated features based on received signals, specifically second order statistics.
• A machine learning network is used to classify each channel of the received signals into a channel profile based on the estimated features.
• Multiple MMSE channel estimation weights are obtained from a database, which stores representative MMSE estimation weights and channel cluster representatives indexed by the estimated features.
• The method applies a respective MMSE channel estimation weight for each channel, improving the accuracy of channel estimation in the communication system.

Abstract

A method includes determining estimated features comprising second order statistics based on at least one received signal. The method also includes classifying, using a machine learning network, each channel of the at least one received signal into a channel profile based on the estimated features. The method also includes obtaining multiple minimum mean square error (MMSE) channel estimation weights from a database based on the estimated features, the database storing (i) representative MMSE estimation weights and (ii) channel cluster representatives indexed by the estimated features. The method also includes applying a respective MMSE channel estimation weight for each channel.

METHOD AND DEVICE FOR STORING AND DISTRIBUTING FILE CONTENT IN MC NETWORK (18449607)

Main Inventor

Arunprasath RAMAMOORTHY

Brief explanation

The abstract describes a method performed by a mission critical data (MCData) message store entity for depositing MCData for file distribution (FD).

• MCData is deposited through an object request message or a retrieve file to store locally request message.
• The messages contain information about the object or object identifier.
• The method retrieves the uniform resource locator (URL) of the file content from a MCData content server.
• The file content is fetched from the MCData content server based on the retrieval result.
• The file content is stored in the MCData user's storage area in the MCData message store entity.
• The object is updated with a URL that references the file content stored in the MCData user's storage area.

Abstract

A method, performed by a mission critical data (MCData) message store entity, of depositing MCData for file distribution (FD). the method includes receiving a MCData deposit an object request message or a MCData retrieve file to store locally request message, wherein the MCData deposit an object request message comprises information regarding the object and the MCData retrieve file to store locally request message comprises information regarding object identifier, based on the MCData deposit an object request message or the MCData retrieve file to store locally request message, retrieving uniform resource locator (URL) of file content in a MCData content server, based on a result of the retrieving, fetching the file content from the MCData content server, storing the file content into a MCData user's storage area in the MCData message store entity, and updating the object with the URL referencing the file content stored in the MCData user's storage area.

SYSTEM AND METHOD OF DISK SHARING FOR CLOUD CONTENT STORAGE (18232300)

Main Inventor

Yang Seok Ki

Brief explanation

The patent application describes a content provider system that includes a repository to store a catalog of content and a storage device with multiple ports.

• The system has a first hosted device connected to the first port and a second hosted device connected to the second port for accessing the storage device.
• The first hosted device executes the content stored in the storage device to provide it to a first user device, while the second hosted device does the same for a second user device.
• One or more processing circuits control access to the storage device from the first and second ports by the hosted devices.
• The system allows for efficient storage and execution of content, providing it to multiple user devices simultaneously.

Abstract

A content provider system includes: a repository to store a catalog of content; a storage device including at least a first port and a second port; a first hosted device connected to the first port over a first storage interface for access to the storage device, and to execute content stored in the storage device to provide the content to a first user device; a second hosted device connected to the second port over a second storage interface for access to the storage device, and to execute the content stored in the storage device to provide the content to a second user device; and one or more processing circuits to control access to the storage device from the first and second ports by the first and second hosted devices.

ELECTRONIC DEVICE COMPRISING ROLLABLE DISPLAY (18328229)

Main Inventor

Minuk KIM

Brief explanation

- The patent application describes an electronic device with a cylindrical housing and a rollable display.

- The device has a first and second side surface portion extending from each end of the cylindrical body. - The rollable display can be pulled from the inside of the housing to the outside and pushed back in. - The device includes radio frequency (RF) transmission lines that run across the rear surface of the rollable display. - There are multiple antennas on one side of the rollable display, connected to the RF transmission lines. - A flexible circuit board is also included, connected to the other side of the RF transmission lines.

Abstract

An electronic device may include a body having a cylindrical shape as a cylindrical housing. The body may include: a first side surface portion extending from one end; and a second side surface portion extending from the other end of the body and disposed in parallel with the first side surface portion. The body may include a rollable display disposed to be rolled in an inner space of the cylindrical housing, and pulled from the inside of the housing to the outside and pushed into the inside of the housing. The electronic device may include radio frequency (RF) transmission lines disposed to traverse an active area of the rollable display on the rear surface of the rollable display. The electronic device may include a plurality of antennas disposed on one side of the rollable display and electrically connected to a first side of the plurality of RF transmission lines. The electronic device may include a flexible circuit board electrically connected to a second side of the RF transmission lines.

ELECTRONIC DEVICE AND METHOD FOR CONTROLLING A CONNECTABLE EXTERNAL DEVICE (18222551)

Main Inventor

Youngjae MEEN

Brief explanation

The abstract describes an electronic device with a display, memory, and communication module. It receives connection information from external devices and displays a user interface for connection approval. It determines control means based on target function information and adds external devices to a connection candidate device list. It displays the list and executes the determined control means based on user input.

• Electronic device with display, memory, and communication module
• Receives connection information from external devices
• Displays a user interface for connection approval
• Determines control means based on target function information
• Adds external devices to a connection candidate device list
• Displays the connection candidate device list
• Executes the determined control means based on user input

Abstract

An electronic device according to various embodiments of the present disclosure comprises a housing, a display, a memory storing an application, a communication module, and at least one processor electrically connected to the display, the memory, and the communication module, the at least one processor receives, through the communication module from at least one external electronic device, connection information including device identification information and target function information, controls, in response to reception of the connection information, the display to display a first user interface for receiving a first user input for connection approval, determines, in response to the first user input, a control means on the basis of the target function information, adds the at least one external electronic device to a connection candidate device list, controls the display to display the connection candidate device list indicating the at least one external electronic device, and executes the determined control means and controls the display to display a second user interface in response to a second user input of selecting the indicator from the connection candidate device list.

ELECTRONIC DEVICE AND METHOD FOR CAPTURING IMAGE BY USING ANGLE OF VIEW OF CAMERA MODULE (18447790)

Main Inventor

Junghoon PARK

Brief explanation

The abstract describes an electronic device with two camera modules.

• The first camera captures an image at a certain angle of view.
• The second camera captures an image at a different angle of view.
• The device has a processor that activates the second camera module when objects in the first image deviate from the first angle of view.

Abstract

An electronic device may include: a first camera module that captures a first image at a first angle of view; a second camera module that captures a second image at a second angle of view different from the first angle of view; and a processor configured to activate the second camera module in response to a case in which at least one of objects detected in the first image deviates from the first angle of view.

PROJECTOR DEVICE AND METHOD FOR CONTROLLING THE SAME (18112098)

Main Inventor

Jiman KIM

Brief explanation

- The patent application is about a projector device and a method for controlling it.

- The device includes a master projector and a slave projector. - The master projector obtains sensing information through both a visible light sensor and an invisible light sensor. - The sensing information helps generate a positional relationship between the master and slave projectors. - The positional relationship is based on the first and second sensing information. - The device also identifies an invisible indicator using the invisible light sensor. - The master projector controls the positional relationship of the slave projector based on the generated positional relationship and the coordinate value of the invisible indicator. - The master projector can project an image stored in its memory onto a projection surface while performing these control functions.

Abstract

The disclosure relates to a projector device and a method for controlling the same. A master projector device according to an embodiment may obtain first sensing information through a visible light sensor, obtain second sensing information through an invisible light sensor, generate a positional relationship with a slave projector device based on the first sensing information and the second sensing information, and control a positional relationship of the slave projector device based on the generated positional relationship and a coordinate value of an invisible indicator identified by the invisible light sensor while projecting an image stored in a memory to a projection surface.

ENCODING METHOD AND APPARATUS THEREFOR, AND DECODING METHOD AND APPARATUS THEREFOR (18328572)

Main Inventor

Narae CHOI

Brief explanation

The patent application describes a method for decoding video by predicting the values of current blocks based on reference samples and interpolation filters.

• Obtains information about the intra prediction mode of a current block from a bitstream.
• Determines the interpolation filter set to be used for predicting the current block based on the size of the block and the intra prediction mode.
• Determines the reference location to which a current sample of the block refers based on the intra prediction mode.
• Selects the interpolation filter from the filter set that corresponds to the reference location.
• Calculates the prediction value of the current sample using the reference samples and the selected interpolation filter.
• Reconstructs the current block based on the prediction value of the current sample.

Abstract

Provided is a video decoding method including: obtaining, from a bitstream, intra prediction mode information indicating an intra prediction mode of a current block; determining an interpolation filter set to be used in prediction of the current block, based on at least one of a size of the current block and the intra prediction mode indicated by the intra prediction mode information; determining a reference location to which a current sample of the current block refers according to the intra prediction mode; determining, in the interpolation filter set, an interpolation filter that corresponds to the reference location; determining a prediction value of the current sample, according to reference samples of the current block and the interpolation filter; and reconstructing the current block, based on the prediction value of the current sample.

DISPLAY DRIVING CIRCUIT AND OPERATING METHOD FOR PERFORMING ENCODING AND DECODING (18233614)

Main Inventor

Jinyong PARK

Brief explanation

The patent application describes a display driver circuit that processes externally-encoded image data using a memory, an internal encoder, and an external decoder.

• The circuit receives externally-encoded image data and processes it using a memory, internal encoder, and external decoder.
• The processed data is then provided to a display device by a source driver.
• The data is processed through the graphic RAM and either the internal decoder or the external decoder, depending on the type of data slice.
• The circuit distinguishes between currently received update slices, recently received standby slices, and still slices.
• The circuit efficiently processes and displays the image data on a display device.

Abstract

A display driver circuit receives externally-encoded image data and processes the data using a memory (graphic RAM), an internal encoder, and an external decoder configured to operate on the externally-encoded image data. The processed data is provided to a display device by a source driver of the display driver circuit. Data is processed through the graphic RAM and an internal decoder or the external decoder depending on whether a slice of the data is a currently received update slice, a recently received standby slice, or a still slice.

DISPLAY APPARATUS, IMAGE PROCESSING APPARATUS AND CONTROL METHOD FOR SELECTING AND DISPLAYING RELATED IMAGE CONTENT OF PRIMARY IMAGE CONTENT (18450084)

Main Inventor

Seong-il KO

Brief explanation

The patent application describes an image processing apparatus that can receive and process primary image content, as well as communicate with a supply source to obtain related image content. 

• The apparatus includes a receiver to receive the primary image content and a communicator to interact with the supply source for obtaining related image content.
• A signal processor is used to process and output the primary image content.
• A controller is responsible for controlling the communicator to request the supply source for related image content and also controls the signal processor to process and play the related image content if the user selects a key to do so while the primary image content is being processed.

Abstract

There is provided an image processing apparatus which comprises a receiver which receives primary image content; a communicator which communicates with at least one supply source which supplies related image content of the primary image content; a signal processor which processes and outputs the primary image content; and a controller which controls the communicator to request the supply source to supply the related image content, and controls the signal processor to process and play the related image content supplied from the supply source in response to the request if a user selects a key to play the related image content of the primary image content while the primary image content received by the receiver is processed by the signal processor.

GENERATION OF DEVICE SETTING RECOMMENDATIONS BASED ON USER ACTIVENESS IN CONFIGURING MULTIMEDIA OR OTHER USER DEVICE SETTINGS (18299544)

Main Inventor

Ho Sub Lee

Brief explanation

- The patent application describes a method for analyzing device usage log data associated with multiple user devices.

- The device usage log data includes information about device settings that can be adjusted by users. - The method also involves obtaining metrics that represent each user's level of customization of device settings. - Based on these metrics, the users are clustered into multiple groups. - At least one of these groups is identified as a valid user group. - The method then provides recommendations for customized device settings to the user devices in the valid user group. - The recommendations are based on the device usage log data associated with the valid user group.

Abstract

A method includes obtaining device usage log data associated with multiple user devices. The device usage log data is related to device settings associated with the user devices, where each device setting associated with the user devices is adjustable by users of the user devices. The method also includes obtaining one or more metrics representing each user's activeness in customizing one or more device settings of the user device associated with the user based on the device usage log data. The method further includes clustering the users into multiple groups based on the metric(s) and identifying at least one of the groups as being at least one valid user group. In addition, the method includes providing one or more recommendations of at least one customized device setting to one or more of the user devices based on the device usage log data associated with the valid user group(s).

LENS ASSEMBLY AND ELECTRONIC DEVICE INCLUDING THE SAME (18204174)

Main Inventor

Yongjae LEE

Brief explanation

The patent application describes a lens assembly that includes multiple lenses aligned along an optical axis, an image sensor, and at least one optical member.

• The lens assembly is designed to guide or condense light onto the image sensor.
• The optical member is positioned between the lenses and the image sensor to receive light from the lenses and refract or reflect the light at least twice.
• The refracted or reflected light is then directed towards the image sensor.
• The ratio between the longer side of the image sensor's imaging surface and the longer side of the emission surface of the closest optical member to the image sensor falls within a specified range.

Abstract

Provided is a lens assembly comprising at least two lenses aligned along a first optical axis; an image sensor configured to receive light guided or condensed through the at least two lenses; and at least one optical member disposed between the at least two lenses and the image sensor to receive light incident through the at least two lenses, and refract or reflect the light at least twice, to guide or emit the light to the image sensor, where a ratio of a longer side of an imaging surface of the image sensor to a longer side of an emission surface of a first optical member closest to the image sensor is within a specified range.

IMAGE-CAPTURING DEVICE AND ELECTRONIC DEVICE INCLUDING SAME (18323822)

Main Inventor

Yongjae LEE

Brief explanation

The patent application describes an image-capturing device with lenses, an image sensor, and optical members.

• The device has lenses arranged along a first optical axis from the object side.
• An image sensor receives light guided through the lenses and has an inclined imaging surface.
• A first optical member is positioned between the lenses and the image sensor.
• The first optical member receives light from the lenses along the first optical axis and emits it along a second optical axis.
• A second optical member is placed between the first optical member and the image sensor.
• The second optical member receives light from the first optical member along the second optical axis and emits it to the image sensor along a third optical axis.

Abstract

An image-capturing device is provided. The image-capturing device includes lenses arranged along a direction of a first optical axis from an object side, an image sensor receiving light guided through the lenses, the image sensor includes an imaging surface inclined with respect to the first optical axis, a first optical member disposed between the lenses and the image sensor, the first optical member receiving light incident through the lenses in a direction of the first optical axis and emitting the light along a direction of a second optical axis crossing the first optical axis, and a second optical member disposed between the first optical member and the image sensor, the second optical member receiving light through the first optical member in the direction of the second optical axis and emitting the light to the image sensor along a direction of a third optical axis crossing the second optical axis.

ELECTRONIC DEVICE INCLUDING CAMERA MODULE AND CONTROL METHOD THEREOF (18324325)

Main Inventor

Jaehyoung PARK

Brief explanation

The patent application describes an electronic device with a lens assembly, image sensor, and processor.

• The electronic device includes a lens assembly that captures light and an image sensor that converts the light into an electrical signal.
• The image sensor has multiple unit pixels, each consisting of a micro-lens and at least two subpixels.
• The processor is connected to the image sensor and processes the electrical signals to generate an image.
• The processor acquires multiple electrical signals from the subpixels and calculates the ratio between them.
• Based on the calculated ratio, the processor determines if flare (unwanted light) is caused by refraction or reflection of the captured light.

Abstract

An aspect of the disclosure provides an electronic device. The electronic device may include a lens assembly, an image sensor including multiple unit pixels configured to convert the light passed through the lens assembly into an electrical signal, and a processor electrically connected to the image sensor to output an image based on the electrical signal. At least one unit pixel included in the multiple unit pixels includes a micro-lens and at least two subpixels formed to correspond to the micro-lens, and the processor is configured to acquire multiple electrical signals from the at least two subpixels, identify a ratio of the multiple electrical signals, and determine, based on the identified ratio, whether flare is generated due to refraction or reflection of the light.

IMAGE CAPTURING METHOD FOR ELECTRONIC DEVICE, AND ELECTRONIC DEVICE THEREFOR (18366434)

Main Inventor

Kwangyong LIM

Brief explanation

The patent application describes an electronic device with a camera that can adjust exposure values and a sensor to detect the image capturing environment. 

• The device has a processor that obtains information about the image capturing environment through the sensor.
• The processor then sets two or more exposure values based on the obtained information.
• Frames are captured with the alternating exposure values.
• Finally, a video file is generated using the captured frames.

Abstract

According to an embodiment of the present disclosure, disclosed is an electronic device comprising: a camera which can set a plurality of exposure values; a sensor for detecting an image capturing environment of the electronic device; and at least one processor electrically connected to the camera and the sensor, wherein the at least one processor is configured to: obtain information about the image capturing environment through the sensor; set two or more exposure values among the plurality of exposure values on the basis of the obtained information about the image capturing environment; obtain frames to which the two or more set exposure values are alternately applied; and generate a video file on the basis of the obtained frames.

COLOR FILTER ARRAY FOR DE-MOSAICING AND BINNING (17664681)

Main Inventor

Tal Michael Feld

Brief explanation

The patent application describes a pixel array for an image sensor with a color filter array (CFA) consisting of multiple cells.

• Each CFA cell is made up of four CFA blocks.
• The first and second CFA blocks contain multiple pixels that sense light of a first color.
• The third CFA block mostly contains pixels that sense a second color, but also includes at least one pixel that senses the first color.
• The fourth CFA block mostly contains pixels that sense a third color, but also includes at least one green pixel that senses the first color.

Abstract

A pixel array of an image sensor includes a plurality of color filter array (CFA) cells. Each of the plurality of CFA cells includes first, second, third, and fourth CFA blocks. Each of the first and second CFA blocks includes a plurality of pixels to sense light of a first color. Most pixels of the third CFA block are configured to sense the second color and the third CFA block includes at least one first pixel to sense the first light. Most pixels of the fourth CFA block are configured to sense a third color of light and the fourth CFA block includes at least one second green pixel to sense the first light.

RGB-NIR PROCESSING AND CALIBRATION (17804096)

Main Inventor

YARDEN SHARABI

Brief explanation

The patent application describes a method for processing images captured by a multi-spectral RGB-NIR sensor. Here are the key points:

• The method starts by receiving a digital image from the RGB-NIR sensor, which captures red, green, blue, and near infra-red (NIR) pixels.
• The NIR contribution to each R, G, and B pixel value is interpolated, resulting in an NIR image.
• The NIR contribution is then subtracted from each R, G, and B pixel value in the original image, creating a decontaminated RGB-NIR image.
• From the decontaminated image, a red, green, and blue (RGB) Bayer image is constructed.
• Finally, the Bayer image is processed to obtain a full-color image.

Key points:

• Method for processing images from a multi-spectral RGB-NIR sensor.
• Interpolation of NIR contribution to each R, G, and B pixel value.
• Subtraction of NIR contribution to obtain a decontaminated RGB-NIR image.
• Construction of a Bayer image from the decontaminated image.
• Processing of the Bayer image to obtain a full-color image.

Abstract

A method for processing images acquired by a multi-spectral RGB-NIR (red/green/blue/near infra-red) sensor includes receiving a RGB-NIR digital image from a multi-spectral RGB-NIR sensor, interpolating an NIR contribution to each R, G and B pixel value, wherein an NIR image is obtained, subtracting the NIR contribution from each R, G and B pixel value in the RGB-NIR digital image wherein a decontaminated RGB-NIR image is obtained, constructing a red, green and blue (RGB) Bayer image from the decontaminated RGB-NIR image, and processing the Bayer image wherein a full color image is obtained. The RGB-NIR digital image includes red (R) pixels, green (G) pixels, blue (B) pixels, and NIR pixels, and every other row in the RGB-NIR digital image includes NIR pixels that alternate with green pixels, and every other row in the RGB-NIR digital image includes green pixels that alternate with red and blue pixels.

ELECTRONIC DEVICE INCLUDING IMAGE SENSOR AND OPERATING METHOD THEREOF (18211665)

Main Inventor

Hwayong KANG

Brief explanation

- The patent application describes an electronic device with an image sensor and a processor.

- The image sensor has a unit pixel and can read out light quantity data multiple times with different conversion gains. - The device can obtain a first image frame by reading out the light quantity data with a lower conversion gain. - The first image frame is then presented to the processor for further processing. - The patent application suggests that there are various other embodiments and possibilities described in the specification.

Abstract

An electronic device of an embodiment of the present document may include an image sensor including a unit pixel, and at least one processor electrically connected to the image sensor. The image sensor may read out light quantity data inputted to the unit pixel twice or more with a first conversion gain, and may read out the light quantity data with a second conversion gain lower than the first conversion gain to obtain a first image frame, and present the first image frame to the at least one processor. In addition to this, various embodiments identified through the specification are possible.

HEADSET HAVING VARIABLE BAND STRUCTURE (18231492)

Main Inventor

Jinwook KIM

Brief explanation

The patent application describes an embodiment of a headset design that includes an ear unit for a speaker, a headband, and two connection members.

• The second connection member is connected to the first connection member and allows the headband to pivot.
• An inclined surface is formed around the second connection member, creating an angled surface with the first connection member.
• The top of the inclined surface is located at the front of the headset.
• The second connection member includes a protrusion that rotates along the surface of the first connection member as the headband pivots.

Abstract

One embodiment according to the present disclosure comprises: an ear unit for accommodating a speaker therein; a head band; a first connection member arranged inside the ear unit; and a second connection member coupled to the head band, wherein: the second connection member comprises a second support member connected to the first connection member so that the head band can pivot, and an inclined surface formed to encompass the second support member and arranged to form an inclined angle with a surface of the first connection member facing same; the top of the inclined surface is formed at the front of a headset; and the second connection member can include a protrusion arranged on one surface of the inclined surface and arranged to rotate along one surface of the first connection member in accordance with the pivoting of the head band.

METHOD AND APPARATUS FOR MONITORING LOCATION AND PROBLEMATIC EVENT OF USER EQUIPMENT (18029749)

Main Inventor

Narendranath Durga TANGUDU

Brief explanation

This patent application describes a method for monitoring the accuracy of location information for a user device in a wireless network. Here are the key points:

• The method involves a Location Management Service (LMS) receiving a request from a server to monitor the location information of a user device.
• The LMS determines the current location information of the user device.
• The LMS sends a response to the server indicating that it accepts the request to monitor the location information.
• The LMS then proceeds to monitor any problematic events related to the user device's location in the wireless network.

Abstract

Accordingly, embodiments herein disclose a method for monitoring deviation in location information of a VAL User Equipment (VAL-UE) in a wireless network. The method includes receiving, by a Location Management Service (LMS) of a Service Enabler Architecture Layer (SEAL) server, a monitor location subscription request from a VAL server. Further, the method includes determining, by the LMS of the SEAL server, the location information of the VAL-UE. Further, the method includes sending, by the LMS, a monitor location subscription response to the VAL server, where the monitor location subscription response indicates that the LMS of the SEAL server accepts the monitor location subscription request to monitor the deviation in the location information of the VAL-UE. Further, the method includes monitoring problematic event(s) of the VAL-UE in the wireless network.

METHOD AND APPARATUS FOR SUPPORTING SECURITY OF ADHOC GROUP CALL IN WIRELESS COMMUNICATION SYSTEM (18324908)

Main Inventor

Hongjin CHOI

Brief explanation

The patent application is about a communication system that supports high data transmission rates in 5G or 6G networks.

• The method involves a first terminal in a wireless communication system.
• The first terminal generates an AGK (Adhoc Group Key) for an adhoc group.
• The first terminal transmits a communication request message to the adhoc group, including a list of IDs of multiple second terminals connected to the first server.
• The first terminal receives a communication return message signed by the first server.
• The first terminal performs encryption and signing operations on the AGK using authentication information related to both the first terminal and the second terminals.
• The first terminal transmits a security material request message for adhoc group communication, including the encrypted and signed AGK.
• The first terminal receives a response message to the security material request, enabling secure communication within the adhoc group.

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A method of a first terminal in a wireless communication system is provided. The method comprising: generating an AGK for an adhoc group; transmitting an adhoc group communication request message including a list including IDs of a plurality of second terminals included in the adhoc group and connected to the first server; receiving an adhoc group communication return message signed by the first server; performing an encryption and signing operation on the AGK based on first authentication information related to the first terminal and the second authentication information; transmitting an adhoc group communication security material request message including the AGK that is encrypted and signed; receiving an adhoc group communication response message in response to transmitting the adhoc group communication security material request message; and performing a secure communication.

DIRECTIONAL SENSING IN CELLULAR SYSTEMS (18194424)

Main Inventor

Jeongho Jeon

Brief explanation

- The patent application describes a system where a user equipment (UE) can indicate its directional sensing capability, such as the number of beams, beam-width, analog or digital beam sweeping, and supported waveforms.

- Based on the UE's indicated capabilities, it can receive a configuration for directional sensing, including the number of beams, maximum or minimum beam-width, reception time between transmission beam sweeping, and waveform. - The UE then performs directional sensing based on the received configuration, which can be either monostatic sensing with reception periods between consecutive sensing signal transmissions or bistatic sensing using multiple beams. - The UE's directional sensing capability may also include the capability of spatial multiplexing of sensing signals with communication signals. - The configuration for directional sensing may allow for the spatial multiplexing of sensing signals with communication signals. - The UE can determine whether to perform spatial multiplexing based on the orthogonality of a desired sensing beam with a beam for communications.

Abstract

Directional sensing capability, including number of beams, beam-width, analog or digital beam sweeping, and supported waveforms, may be indicated by a user equipment (UE), which may then receive a configuration for directional sensing including number of beams, maximum or minimum beam-width, reception time between transmission beam sweeping, and waveform. The UE then performs directional sensing based on the received configuration. The configuration for directional sensing may be for one of monostatic sensing with reception periods between consecutive sensing signal transmissions or bistatic sensing using a plurality of beams. The UE's directional sensing capability may include capability of spatial multiplexing of sensing signals with communication signals. The configuration for directional sensing may permit spatial multiplexing of sensing signals with communication signals. The UE may determine to perform spatial multiplexing of sensing signals with communication signals based on orthogonality of a desired sensing beam with a beam for communications.

MEASUREMENT REPORT METHOD FOR FREQUENCY SELECTION OF ELECTRONIC DEVICE, AND ELECTRONIC DEVICE (18365605)

Main Inventor

Junsuk KIM

Brief explanation

The abstract describes an electronic device that measures the downlink performance of a second communication network while connected to a first base station of a first communication network. 

• The device confirms specified measurement objects (MOs) for measuring the downlink performance of the second communication network.
• It determines measurement priorities for the specified MOs based on information stored in the memory relating to the transmission/reception performance of signals.
• The device measures the reception signal strength of at least one MO from a signal transmitted by a second base station of the second communication network, based on the measurement priorities.
• It controls the electronic device to transmit at least one measurement report (MR) to the first base station of the first communication network based on the measurement result of the reception signal strength for the at least one MO.

Abstract

An electronic device according to various embodiments comprises: a memory and at least one communication processor, the at least one communication processor configured to: confirm a plurality of specified measurement objects (MOs) for measuring the downlink performance of a second communication network, while connected to a first base station of a first communication network; confirm measurement priorities of the plurality of specified MOs based at least on information relating to the transmission/reception performance of signals having a frequency corresponding to the respective plurality of MOs and stored in the memory; measure the reception signal strength with respect to at least one MO from a signal transmitted from a second base station of the second communication network, based on the measurement priorities of the plurality of MOs; and control the electronic device to transmit at least one measurement report (MR) to the first base station of the first communication network, on the basis of the measurement result of the reception signal strength with respect to the at least one MO.

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING DATA IN WIRELESS COMMUNICATION SYSTEM (18449289)

Main Inventor

Kisuk KWEON

Brief explanation

This patent application describes a method for performing communication in a wireless communication system using a network exposure function (NEF).

• The method involves receiving a connection establishment request from a session management function (SMF) after a protocol data unit (PDU) session establishment procedure between the SMF and a user equipment (UE).
• A non-internet protocol (IP) data delivery (NIDD) configuration procedure is then performed based on NIDD configuration information included in the connection establishment request.
• The NIDD configuration procedure is performed between the NEF and an application function (AF) on the UE.
• Once the NIDD configuration procedure is completed, a connection is established between the SMF and the NEF.
• Finally, a connection establishment response is transmitted back to the SMF.

Abstract

A method of performing communication, by a network exposure function (NEF), in a wireless communication system is provided. The method includes receiving a connection establishment request from a session management function (SMF), based on a protocol data unit (PDU) session establishment procedure performed between the SMF and a user equipment (UE), performing a non-internet protocol (IP) data delivery (NIDD) configuration procedure according to NIDD configuration information included in the connection establishment request, based on whether the NIDD configuration procedure is previously performed on the UE between the NEF and an application function (AF), establishing connection between the SMF and the NEF, and transmitting a connection establishment response to the SMF.

METHOD AND APPARATUS FOR TRANSMITTING DATA IN A MOBILE COMMUNICATION SYSTEM (18449639)

Main Inventor

Jaehyuk JANG

Brief explanation

- The patent application is about a communication method and system that combines 5G technology with Internet of Things (IoT) technology.

- The purpose of this invention is to support higher data rates than the previous 4G system and enable intelligent services in various areas such as smart home, smart city, and healthcare. - The invention focuses on efficiently allocating uplink transmission resources to the data of a terminal, ensuring quick and effective communication.

Abstract

The present disclosure relates to a communication method and system for converging a 5th-Generation (5G) communication system for supporting higher data rates beyond a 4th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present disclosure relates to a method for quickly and efficiently allocating uplink transmission resource to data of a terminal.

SYSTEM AND METHOD FOR CONNECTION MANAGEMENT (18365061)

Main Inventor

Koustav ROY

Brief explanation

This patent application describes a system and method for managing connections in a 5G network. Here are the key points:

• The method involves a user equipment (UE) establishing a connection with a 5G cell in a specific area.
• The UE then determines if there are any Long-Term Evolution (LTE) cells in that area that it cannot access.
• LTE cells operate on a different frequency than 5G cells.
• If the UE finds LTE cells that it cannot access, it temporarily deprioritizes or disables a Stand Alone (SA) mode.
• The SA mode is a specific mode of operation for the UE.
• This deprioritization or disabling is based on the presence of inaccessible LTE cells in the area.
• The purpose of this method is to optimize the UE's connection management in areas where both 5G and LTE cells are present.

Abstract

The present disclosure relates to a system and a method for connection management. The method includes establishing, by a UE, a connection with a 5G cell. The established connection with the 5G cell is in a current tracking area of a 5G New Radio (NR). Further, the method includes determining, by the UE, one or more Long-Term Evolution (LTE) cells in the current tracking area or registration area that are not accessible to the UE (). The one or more LTE cells are configured to operate on an LTE frequency. Furthermore, the method includes temporarily deprioritising or disabling, by the UE, a Stand Alone (SA) mode based on the determination of the one or more LTE cells in the current tracking area or the registration area that are not accessible to the UE.

NODES, USER EQUIPMENTS AND METHODS THEREOF (18033198)

Main Inventor

Weiwei WANG

Brief explanation

The patent application describes an application that operates in a wireless communication system.

• The application includes nodes and user equipment that perform various functions.
• One method performed by a first node involves sending a message to a second node.
• The message contains information about activating or deactivating a secondary cell group (SCG).
• The SCG is a group of cells that can be used for communication purposes.
• The application provides configuration information related to the SCG activation/deactivation process.

Abstract

This application provides nodes, user equipment, and methods performed by the nodes and user equipment in a wireless communication system. A method performed by a first node includes transmitting a first message to a second node, wherein the first message includes configuration information related to activation/deactivation of a secondary cell group (SCG).

METHOD FOR SUPPORTING HANDOVER AND CORRESPONDING APPARATUS (18449644)

Main Inventor

Lixiang XU

Brief explanation

- The patent application is about a communication method and system that combines 5G technology with Internet of Things (IoT) technology.

- It aims to support higher data rates than the previous 4G system and enable intelligent services in various areas such as smart home, smart city, and healthcare. - The application specifically focuses on a method for a base station to support a smooth transition from an evolved packet system (EPS) to a 5G system. - The disclosed methods address the issue of data forwarding when a user equipment (UE) moves between an LTE system and a 5G system. - These methods ensure that data loss is avoided and the continuity of services is maintained during the handover process.

Abstract

The present disclosure relates to a communication method and system for converging a 5-Generation (5G) communication system for supporting higher data rates beyond a 4-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. The present application provides a method of a base station for supporting an inter-system handover from an evolved packet system (EPS) system to a 5th generation (5G) system. Disclosed methods solve the data forwarding problem during the movement of a UE between an LTE system and a 5G system, so that the loss of data is avoided and the continuity of services is ensured.

BASE STATION AND METHOD FOR SUPPORTING SELF-CONFIGURATION AND SELF-OPTIMIZATION (18325580)

Main Inventor

Lixiang XU

Brief explanation

- This patent application is about a communication system that supports a higher data transmission rate, specifically for 5G or 6G networks.

- The system includes a base station and a method for self-configuration and self-optimization. - The method involves several steps:

 * The main node (MN) sends a request message to add a secondary node (SN) to a target candidate SN.
 * The MN receives an acknowledgment message from the target candidate SN.
 * The MN sends a radio resource control (RRC) reconfiguration message to a user equipment (UE).
 * The MN receives an RRC reconfiguration complete message from the UE, indicating successful reconfiguration after accessing a candidate secondary cell group primary cell (PS Cell).
 * The MN sends a request message to release the SN to a source SN.
 * The MN receives an acknowledgment message from the source SN, which includes secondary cell group (SCG) UE history information.
 * The MN updates its saved UE history information based on the received information.
 * The MN sends the UE history information to the target SN.

- The innovation in this patent application lies in the method for self-configuration and self-optimization of the communication system, which enables efficient addition and release of secondary nodes and ensures seamless transmission for user equipment.

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. A base station and a method for supporting self-configuration and self-optimization are provided. The method includes sending, by a main node (MN), a secondary node (SN) addition request message to a target candidate SN, receiving, by the MN, an addition request acknowledgment message from the target candidate SN, sending, by the MN, a radio resource control (RRC) reconfiguration message to a user equipment (UE), receiving, by the MN, an RRC reconfiguration complete message from the UE, which is an RRC reconfiguration complete message sent by the UE after accessing a candidate secondary cell group primary cell (PS Cell), sending, by the MN, an SN release request message to a source SN, receiving, by the MN, an SN release request acknowledgment message from the source SN, wherein the release request acknowledgment message includes secondary cell group (SCG) UE history information, updating, by the MN, saved UE history information, sending, by the MN, UE history information to a target SN.

METHOD AND APPARATUS FOR UE INFORMATION DELIVERY FOR NETWORK ENERGY SAVING (18325577)

Main Inventor

Sangkyu BAEK

Brief explanation

The abstract describes a method performed by a terminal in a wireless communication system. Here is a simplified explanation of the abstract:

• The method involves a terminal receiving a first message from a base station.
• The first message is associated with triggering the transmission of a second message.
• The terminal then identifies whether the transmission of the second message, which is related to network energy saving, is triggered based on the first message.
• If the transmission of the second message is triggered, the terminal transmits the second message to the base station.
• Finally, the terminal receives a third message from the base station, which is associated with the network energy status of the base station and is configured based on the second message.

Bullet points explaining the patent/innovation:

• The method enables a terminal in a wireless communication system to trigger the transmission of a message related to network energy saving.
• This allows the terminal to actively participate in energy-saving measures within the network.
• By receiving a message from the base station and determining whether to transmit a network energy-saving message, the terminal can contribute to reducing energy consumption in the system.
• The method also allows the terminal to receive information about the network energy status of the base station, which can help in making energy-efficient decisions.
• Overall, this innovation aims to improve energy efficiency in wireless communication systems by involving the terminal in network energy-saving measures.

Abstract

A method performed by a terminal in a wireless communication system. The method includes receiving, from a base station, a first message associated with triggering a transmission of a second message, identifying whether the transmission of the second message associated with network energy saving is triggered based on the first message, transmitting, to the base station, the second message associated with network energy saving, in case that the transmission of the second message is triggered, and receiving, from the base station, a third message associated with a network energy status of the base station configured based on the second message.

METHOD AND DEVICE FOR SIGNAL TRANSMISSION (18324919)

Main Inventor

Qi LI

Brief explanation

- The patent application is related to a communication system that supports a higher data transmission rate, specifically in the context of 5G or 6G technology.

- The method described in the patent involves a user equipment (UE) performing certain actions in the communication system. - The UE determines a power headroom report (PHR) and/or a transmission signal power based on first information. - The UE then transmits the PHR and/or transmits a signal with the determined transmission signal power. - The purpose of this method is to improve the efficiency and effectiveness of data transmission in the communication system. - The patent application does not provide any additional details or information about the specific implementation or technical aspects of the method.

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate. The present disclosure provides a method performed by a user equipment in a communication system, including: determining a power headroom report (PHR) and/or a transmission signal power based on first information; and transmitting the PHR and/or transmitting a signal with the transmission signal power.

DEVICE AND METHOD FOR UPLINK POWER CONTROL IN WIRELESS COMMUNICATION SYSTEM (18446853)

Main Inventor

Namhoon KIM

Brief explanation

- The patent application is related to a communication system that supports a higher data transmission rate than the current 4G LTE system.

- The system is specifically focused on 5G or pre-5G technology. - The method described in the patent application is for operating a user equipment (UE) in a wireless communication system. - The UE receives downlink control information from a base station, which includes a transmit power control (TPC) command. - If the UE is using an unrestricted TPC configuration and has reached its maximum transmit power, the method proceeds. - The power control value, which depends on the TPC command, is a positive value. - Based on this power control value, the UE determines its uplink transmit power. - The UE then transmits an uplink signal using the determined uplink transmit power.

Abstract

The disclosure relates to a 5generation (5G) or pre-5G communication system for supporting a higher data transmission rate than a 4Generation (4G) communication system, such as long term evolution (LTE). A method of operating a user equipment (UE) in a wireless communication system is provided. The method includes receiving, from a base station, downlink control information including a transmit power control (TPC) command, if the UE is related to an unrestricted TPC configuration, the UE reaches maximum transmit power, and a power control value depending on the TPC command is a positive value, determining uplink transmit power, based on the power control value, and transmitting an uplink signal, based on the determined uplink transmit power.

APPARATUS AND METHOD FOR NETWORK SLICE CONTROL IN COMMUNICATION SYSTEM (18448660)

Main Inventor

Sunil KUMAR

Brief explanation

The abstract describes a method performed by a network device in a communication system. Here is a simplified explanation of the abstract:

• The method involves a network device receiving an access request message from a terminal for a network slice.
• The network device obtains the external network identifier of the terminal from a unified data repository (UDR).
• The network device then receives information from an external network server on whether to allow the terminal access to the network slice based on its external network identifier.
• Finally, the network device transmits an access control response message to the access and mobility management function (AMF).

Bullet points explaining the patent/innovation:

• The method allows a network device to handle access requests from terminals for specific network slices.
• By obtaining the external network identifier of the terminal from a unified data repository, the network device can uniquely identify the terminal.
• The network device then communicates with an external network server to determine whether the terminal should be granted access to the requested network slice.
• This approach enables efficient and secure access control for network slices in a communication system.
• The method improves the overall management and control of network resources by ensuring that only authorized terminals can access specific network slices.

Abstract

A method performed by a network device in a communication system is provided. The method includes the steps of receiving an access request message of a terminal for a network slice from an access and mobility management function (AMF), obtaining, from a unified data repository (UDR), an external network identifier of the terminal, receiving, from an external network server, information on whether to allow the terminal access to the network slice on the basis of the external network identifier of the terminal, and transmitting an access control response message to the AMF.

METHOD AND DEVICE FOR MOBILE HOT SPOT AUTO BAND SELECTION (18324738)

Main Inventor

Saranappa Raj Kumar

Brief explanation

This patent application describes methods for a user equipment (UE) to select a frequency band in a mobile hotspot (MHS) scenario. The UE determines various parameters such as signal strength, connectivity conditions, and data consumption capability. These parameters are then mapped to identifiers such as cell ID, AP ID, and geolocation while connecting with a client device. Based on this mapping, the UE selects a frequency band from a range of options.

• The patent application focuses on methods for a UE to select a frequency band in a mobile hotspot scenario.
• The UE determines parameters such as signal strength, connectivity conditions, and data consumption capability.
• These parameters are mapped to identifiers like cell ID, AP ID, and geolocation during the connection with a client device.
• The UE then uses this mapping to select the most suitable frequency band from a range of options.

Abstract

Embodiments herein disclose methods for selecting a frequency band in (MHS) for a UE. These methods may include determining, by the UE, one or more parameters, wherein the one or more parameters may include at least one of: signal strength parameters, connectivity conditions of the UE in relation to the client device, and a data consumption capability of the UE, then mapping, by the UE, one or more parameters of the UE to at least one of a cell identity (ID), an Access point ID in case of Wi-Fi sharing (AP ID), and a geolocation of the UE, while connecting with the client device, and selecting, by the UE, the frequency band from a plurality of frequency bands based on at least one of the mapped cell ID or application ID and the geolocation of the UE.

METHOD AND APPARATUS FOR TRAFFIC URGENCY INDICATION (18322501)

Main Inventor

Peshal Nayak

Brief explanation

The patent application is about methods and apparatuses for supporting traffic urgency indication in wireless communication.

• The method involves a non-AP device forming a link with an AP (access point).
• The non-AP device transmits information related to a traffic transmission to the AP, including a scheduling parameter that helps the AP make a scheduling decision.
• The non-AP device receives data associated with the scheduling parameter from the AP.
• Based on the received data, the non-AP device determines whether to transmit the traffic transmission to the AP.

Abstract

Methods and apparatuses for supporting traffic urgency indication. A method for wireless communication performed by a non-access point (AP) device that comprises a first station (STA), comprises forming a link with a first AP; transmitting information associated with a traffic transmission to the first AP, the information including a scheduling parameter configured to aid the first AP in making a scheduling decision; receiving data associated with the scheduling parameter from the first AP; and based on the received data, determining to transmit the traffic transmission to the first AP.

METHOD AND DEVICE FOR SUPPORTING MULTICAST/BROADCAST SERVICE IN MOBILE COMMUNICATION SYSTEM (18249531)

Main Inventor

Donggun KIM

Brief explanation

- The patent application is related to a 5G communication system that supports higher data transmission rates compared to 4G systems like LTE.

- The patent application describes a method for a terminal to support a multicast/broadcast service (MBS) in a wireless communication system. - The method involves receiving a radio resource control (RRC) message from a base station, which instructs the terminal to switch from a multicast service (point-to-multicast) to a unicast service (point-to-point). - Upon receiving the RRC message, the terminal initializes at least one window parameter based on the received packet data convergence protocol (PDCP) data. - The method aims to optimize the transmission of data in a multicast/broadcast service by switching to a unicast service when necessary and adjusting window parameters accordingly.

Abstract

The present disclosure relates to a 5G communication system for supporting a higher data transmission rate than a 4G communication system such as LTE. The present disclosure provides a method of a terminal supporting a multicast/broadcast service (MBS) in a wireless communication system. The method may comprise the steps of: receiving, from a base station, a radio resource control (RRC) message indicating to switch from a multicast service (point-to-multicast (PTM)) to a unicast service (point-to-point (PTP)); and initializing at least one window parameter on the basis of received packet data convergence protocol (PDCP) data.

QoS SUPPORT FOR P2P COMMUNICATION (18318634)

Main Inventor

Rubayet Shafin

Brief explanation

This patent application is about methods and devices that support Quality of Service (QoS) for peer-to-peer (P2P) communication in wireless networks. The method described involves a non-access point (AP) device, which includes a first station (STA), performing the following steps:

• Forming a link with a first AP: The non-AP device establishes a connection with an access point (AP) in the wireless network.
• Forming a P2P link with a second non-AP STA: The non-AP device establishes a direct peer-to-peer connection with another non-AP device in the network.
• Transmitting a request associated with a transmit opportunity (TXOP) to the AP: The non-AP device sends a request to the AP, indicating its desire to transmit data during a specific time period known as the transmit opportunity (TXOP).
• Receiving information associated with the TXOP from the AP: The non-AP device receives information from the AP regarding the TXOP, which includes details about the available time and resources for data transmission.
• Determining the usability of the received TXOP information: The non-AP device evaluates whether the received TXOP information can be used for both uplink communication (transmitting data to the AP) and P2P communication (transmitting data directly to another non-AP device), or if it can only be used for uplink communication.

Overall, this patent application describes a method and apparatus that enables non-AP devices to establish P2P communication while also ensuring QoS support by efficiently utilizing the available transmit opportunities in a wireless network.

Abstract

Methods and apparatuses for supporting QoS support for P2P communication. A method for wireless communication performed by a non-access point (AP) device that includes a first station (STA) comprises: forming a link with a first AP; forming a first peer-to-peer (P2P) link with a second non-AP STA; transmitting a request associated with a transmit opportunity (TXOP) to the AP; receiving information associated with the TXOP from the AP; and determining whether the received information associated with the TXOP can be used only for uplink communication or for both uplink communication and P2P communication.

METHOD AND APPARATUS FOR UPLINK TRANSMISSIONS IN FRAME-BASED EQUIPMENT NR UNLICENSED (18447960)

Main Inventor

Yingzhe Li

Brief explanation

This patent application describes methods and apparatuses for operating base stations (BSs) and user equipment (UE) in a wireless communication system. The focus is on utilizing a shared spectrum channel efficiently.

• The UE receives a first DCI (Downlink Control Information) from a BS over the shared spectrum channel.
• The first DCI includes a COT (Channel Occupancy Time) of the BS, which is divided into a first portion for downlink transmission and a second portion for uplink transmission.
• There is a gap between the first and second portions of the COT.
• The UE determines the duration of the gap and performs a channel access procedure based on it.
• During the gap, the UE senses the shared spectrum channel to check if it is idle.
• If the channel is sensed as idle, the UE transmits the uplink transmission in the second portion of the COT.
• The UE receives the downlink transmission in the first portion of the COT.

Overall, this patent application proposes a method for efficient channel access and transmission scheduling in a wireless communication system, ensuring optimal utilization of the shared spectrum channel.

Abstract

Methods and apparatuses of a BSs and UEs in a wireless communication system are provided. A method of operating the UE comprises: receiving, from a BS over a shared spectrum channel, a first DCI including a COT of the BS; determining a first portion of the COT for a downlink transmission from the BS and a second portion of the COT for an uplink transmission to the BS, wherein the COT includes a gap between the first and second portions of the COT; performing a channel access procedure based on a duration of the gap; receiving the downlink transmission in the first portion of the COT; and transmitting the uplink transmission in the second portion of the COT based on a sensing status of the shared spectrum channel that is sensed as an idle state during the channel access procedure in the duration of the gap.

METHOD AND DEVICE FOR DETECTING UPLINK LBT FAILURE IN WIRELESS COMMUNICATION SYSTEM USING UNLICENSED BAND (18449317)

Main Inventor

Jaehyuk JANG

Brief explanation

- The patent application is about a communication technique that combines 5G and IoT technology to support higher data transmission rates.

- The technique can be used in various intelligent services such as smart homes, smart buildings, smart cities, smart cars, healthcare, digital education, retail business, and security and safety-related services. - The patent application specifically focuses on a method and apparatus for detecting an uplink listen-before-talk (LBT) failure in a wireless communication system using 3GPP 5G new radio (NR) technology.

Abstract

The disclosure relates to a communication technique for convergence of a 5G communication system for supporting a higher data transmission rate beyond a 4G system with an IoT technology, and a system therefor. The disclosure may be applied to intelligent services (e.g., smart homes, smart buildings, smart cities, smart cars or connected cars, health care, digital education, retail business, security and safety-related services, etc.) based on 5G communication technology and IoT-related technology. The disclosure relates to a method and apparatus for detecting an uplink listen-before-talk (LBT) failure when using a 3GPP 5G new radio (NR) technology in a wireless communication system.

ELECTRONIC DEVICE FOR SWITCHING CONNECTION OF DEVICE TO DEVICE COMMUNICATION (18306611)

Main Inventor

Buseop JUNG

Brief explanation

This patent application describes an electronic device and a method for operating the device. The device includes a communication circuit and a processor connected to the communication circuit. The processor is designed to perform various functions related to data transmission and reception between the device and an external electronic device connected to an access point (AP).

• The device can receive information about the external electronic device's first communication scheme for data transmission and reception.
• The device can set up a first session with the external electronic device based on the information received about the first communication scheme.
• The device can also receive information about the external electronic device's second communication scheme, which is different from the first communication scheme.
• The device can discover the external electronic device based on the information about the second communication scheme, but only if the device meets a predetermined condition.
• The device can then set up a second session with the external electronic device based on data related to the second communication scheme.
• Finally, the device can transmit and/or receive data through the second session.

Overall, this patent application describes a method for an electronic device to establish different communication sessions with an external electronic device, based on the specific communication schemes supported by the external device.

Abstract

An electronic device and a method of operating an electronic device are provided. The device includes a communication circuit and a processor operatively connected to the communication circuit. The processor is configured to receive, in a connected state with an access point (AP), information on an external electronic device related to a first communication scheme for data transmission and/or reception between the external electronic device connected to the AP and the electronic device and information on the external electronic device related to a second communication scheme different from the first communication scheme, set up a first session supported by the first communication scheme with the external electronic device, based on the information on the external electronic device related to the first communication scheme, discover the external electronic device, based on the information on the external electronic device related to the second communication scheme according to the electronic device satisfying a predetermined condition, set up a second session, based on data related to the second communication scheme, and transmit and/or receive the data through the second session.

METHOD AND APPARATUS TO OPTIMIZE RANDOM ACCESS IN WIRELESS COMMUNICATION SYSTEM (18322036)

Main Inventor

Sangbum KIM

Brief explanation

- The patent application is about a communication system that supports a higher data transmission rate, specifically for 5G or 6G systems.

- The method described in the patent involves a user equipment (UE) in a wireless communication system. - The UE receives a radio resource control (RRC) release message from a base station, which includes information for a small data transmission (SDT) configuration. - The UE then transmits small data to the base station based on the information received. - Additionally, the UE transmits a random access (RA) report to the base station, which includes SDT information. - The invention aims to improve data transmission rates in wireless communication systems by utilizing SDT configurations and efficient RA reporting.

Abstract

The disclosure relates to a fifth generation (5G) or sixth generation (6G) communication system for supporting a higher data transmission rate. More specifically, the disclosure relates to a method performed by a user equipment (UE) in a wireless communication system, including receiving, from a base station, a radio resource control (RRC) release message including first information for a small data transmission (SDT) configuration, transmitting, to the base station, small data based on the first information, and transmitting, to the base station, a random access (RA) report including SDT information.

METHOD AND APPARATUS FOR ENHANCED CONNECTED MODE DISCONTINUOUS RECEPTION IN WIRELESS COMMUNICATION SYSTEM (18326572)

Main Inventor

Hyunjeong KANG

Brief explanation

The patent application is about a communication system that supports a higher data transmission rate and improves the connected mode DRX (Discontinuous Reception) functionality. It also addresses the handling of a timer for an SDT (Short Data Transmission) procedure in a wireless communication system.

• The patent application is related to a 5G or 6G communication system.
• It focuses on enhancing the connected mode DRX functionality.
• The system aims to support a higher data transmission rate.
• It also addresses the handling of a timer for an SDT procedure.
• The innovation is designed for use in a wireless communication system.

Abstract

The disclosure relates to a 5G or 6G communication system for supporting a higher data transmission rate, i.e., a connected mode DRX enhancement, and handling a timer for an SDT procedure in a wireless communication system.

HOME APPLIANCE AND POWER TRANSMISSION APPARATUS FOR DETECTING EMPTY HEATING (18326564)

Main Inventor

Jaejin KIM

Brief explanation

The abstract describes a wireless power transmission apparatus that can determine if a cooking appliance is undergoing empty heating.

• The apparatus includes a processor and a communication interface to interact with the cooking appliance.
• The communication interface receives temperature data from the cooking appliance, including the temperature of the bottom surface and the internal temperature.
• The processor analyzes the temperature data for two time periods: during a heating operation and after the heating operation is stopped.
• The processor stops the heating operation for the second time period.
• Based on the relationship between the temperature of the bottom surface and the internal temperature during the second time period, the processor determines if the cooking appliance is undergoing empty heating.
• This technology can help prevent energy waste and potential damage to the cooking appliance by detecting when it is heating without any food or liquid inside.

Abstract

A wireless power transmission apparatus for determining empty heating is provided. The wireless power transmission apparatus includes at least one processor configured to control a communication interface configured to communicate with a cooking appliance, wherein the communication interface is further configured to receive, from the cooking appliance, a temperature of a bottom surface of the cooking appliance and an internal temperature of the cooking appliance for a first time period during which a heating operation is performed and for a second time period following the first time period, during which the heating operation is stopped, and the at least one processor is further configured to stop the heating operation for the second time period, and determine whether the cooking appliance undergoes empty heating based on a relationship between the temperature of the bottom surface and the internal temperature for the second time period.

ELECTRONIC DEVICE INCLUDING SLIDING STRUCTURE AND FLEXIBLE DISPLAY (18446436)

Main Inventor

Hyoungtak CHO

Brief explanation

The patent application describes an electronic device with a flexible display that can slide in and out of the device.

• The device has two housings, with the second housing able to slide relative to the first housing.
• There are supports in each housing, with the flexible display attached to the first support.
• The flexible display has a visible area on the outside of the device and a second area that can be withdrawn or inserted into the device while being supported by the second support.
• The device also includes a motor assembly connected to the second support, which provides the force for sliding the second housing.
• A thermal conductive member is placed on the first support, and when the second area of the flexible display is inserted into the device, it comes into contact with a bracket on the second support, which is in turn in contact with the thermal conductive member.

Abstract

According to an embodiment of the disclosure, an electronic device may include: a first housing, a second housing, a first support, a second support, a flexible display, a motor assembly including a motor, and a first thermal conductive member including a thermally conductive material. The second housing may be slidable relative to the first housing. The first support may be positioned in the first housing. The second support may be positioned in the second housing. The flexible display may include a first area and a second area configured to extend from the first area. The first area may be disposed on the first support and be configured to be visible to the outside of the electronic device. The second area may be configured to, during sliding of the second housing, be withdrawn from or inserted into an inner space of the electronic device while being supported by the second support. The motor assembly may be connected to the second support through a bracket disposed on the second support and be configured to provide a drive force for sliding of the second housing. The first thermal conductive member may be disposed on the first support. Based on the second area being inserted in the inner space of the electronic device, the bracket may be configured to be in contact with the first thermal conductive member.

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME (18076963)

Main Inventor

Seung Min SONG

Brief explanation

The patent application describes a semiconductor device with a substrate and active patterns that extend in a first direction.

• The device includes a gate structure that extends in a second direction intersecting the first direction.
• There is also a cutting pattern on the substrate to cut the gate structure.
• The gate structure includes a lower gate electrode, an upper gate electrode, and an insulating pattern.
• The lower active pattern penetrates through the lower gate electrode, and the upper active pattern penetrates through the upper gate electrode.
• The insulating pattern is arranged with the upper gate electrode along the second direction.

Abstract

A semiconductor device includes a substrate, a lower active pattern which is spaced apart from the substrate and extends in a first direction, an upper active pattern on the lower active pattern, the upper active pattern being spaced apart from the lower active pattern and extending in the first direction, a gate structure on the substrate, the gate structure extending in a second direction intersecting the first direction, and a cutting pattern on the substrate, the cutting pattern extending in the first direction to cut the gate structure. The gate structure includes a lower gate electrode through which the lower active pattern penetrates, an upper gate electrode which is connected to the lower gate electrode and through which the upper active pattern penetrates, and an insulating pattern on one side of the cutting pattern, the insulating pattern being arranged with the upper gate electrode along the second direction.

INTEGRATED CIRCUIT INCLUDING STATIC RANDOM ACCESS MEMORY DEVICE (18201465)

Main Inventor

Eo Jin Lee

Brief explanation

The abstract describes an integrated circuit that includes a static random access memory (SRAM) device.

• The SRAM device consists of an SRAM unit cell with multiple transistors connected to output nodes.
• The first output node is connected to various components such as gate electrodes, connection wiring lines, and active contacts.
• The layout of these components forms a specific shape called a "first fork shape".

Abstract

An integrated circuit includes a static random access memory (SRAM) device. The SRAM device includes an SRAM unit cell that includes a first output node to which a first pull-up transistor, a first pull-down transistor, and a second pull-down transistor are commonly connected, and a second output node to which a second pull-up transistor, a third pull-down transistor, and a fourth pull-down transistor are commonly connected. The first output node is connected to a first gate electrode, a second gate electrode, a first connection wiring line, a first node formation pattern, and a first active contact, and a layout of the first output node, the first gate electrode, the second gate electrode, the first connection wiring line, the first node formation pattern, and the first active contact forms a first fork shape.

SEMICONDUCTOR DEVICE (18144885)

Main Inventor

Byeongjoo Ku

Brief explanation

The patent application describes a semiconductor device that includes various components such as a substrate, bit lines, a mold insulating layer, channel layers, word lines, and a trimming insulating block.

• The device has a substrate with different areas for cell array, periphery circuit, and interface.
• Bit lines are arranged in the cell array area and extend in a horizontal direction.
• A mold insulating layer is placed on the bit lines and has openings in a different horizontal direction.
• Channel layers are located on the bit lines within each opening of the mold insulating layer.
• Word lines are positioned on the channel layers and extend from the cell array area to the interface area.
• The word lines consist of a first word line on one side of each opening and a second word line on the other side.
• A trimming insulating block is present in the interface area and connected to the ends of the first and second word lines.

Abstract

A semiconductor device includes: a substrate including a cell array area, a periphery circuit area, and an interface area; bit lines arranged in the cell array area and extending in a first horizontal direction; a mold insulating layer arranged on the bit lines and including openings extending in a second horizontal direction; channel layers respectively arranged on the bit lines in each of the openings; word lines respectively arranged on the channel layers and extending in the second horizontal direction from the cell array area to the interface area, the word lines including a first word line on a first sidewall of each opening of the mold insulating layer and a second word line on a second sidewall of the opening; and a trimming insulating block arranged in the interface area and connected to an end of the first word line and an end of the second word line.

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME (18171171)

Main Inventor

SEOKHAN PARK

Brief explanation

The patent application describes a semiconductor device with bit line structures on a substrate.

• The bit line structures extend in one direction and are spaced apart from each other in another direction.
• Semiconductor patterns are placed on each bit line structure, with insulating interlayer patterns between them.
• Word lines are also placed on the bit line structures, adjacent to the semiconductor patterns.
• Capacitors are connected to the semiconductor patterns.
• Each insulating interlayer pattern has a seam extending in the second direction.

Abstract

A semiconductor device includes bit line structures on a substrate. Each bit line structure extends in a second direction, and the bit line structures are spaced apart from each other in a first direction. The semiconductor device further includes semiconductor patterns spaced apart from each other in the second direction on each of the bit line structures, insulating interlayer patterns between neighboring ones of the semiconductor patterns in the first direction, and word lines spaced apart from each other in the second direction on the bit line structures. Each word line extends in the first direction adjacent to the semiconductor patterns. The semiconductor device further includes capacitors disposed on and electrically connected to the semiconductor patterns, respectively. A seam extending in the second direction is formed in each of the insulating interlayer patterns.

SEMICONDUCTOR DEVICE (18200135)

Main Inventor

Jeonil LEE

Brief explanation

The patent application describes a semiconductor device with a specific structure and configuration. 

• The device includes a single crystal semiconductor pattern with a first source/drain region, a second source/drain region, and a first vertical channel region between them.
• The second source/drain region is positioned at a higher level than the first source/drain region.
• There is a first gate electrode that faces one side surface of the single crystal semiconductor pattern.
• A first gate dielectric layer is present between the single crystal semiconductor pattern and the first gate electrode.
• The device also includes a complementary structure that contacts the second side surface of the single crystal semiconductor pattern.
• The complementary structure consists of an oxide semiconductor layer.

Abstract

A semiconductor device includes a first single crystal semiconductor pattern including a first source/drain region, a second source/drain region, and a first vertical channel region between the first source/drain region and the second source/drain region, the second source/drain region being at a higher level than the first source/drain region; a first gate electrode facing a first side surface of the first single crystal semiconductor pattern; a first gate dielectric layer, the first gate dielectric layer including a portion between the first single crystal semiconductor pattern and the first gate electrode; and a complementary structure in contact with a second side surface of the first single crystal semiconductor pattern, wherein the complementary structure includes an oxide semiconductor layer.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME (18093568)

Main Inventor

Eunjung KIM

Brief explanation

The patent application describes a semiconductor memory device with active patterns arranged in a grid-like pattern.

• The active patterns have a central portion, a first end portion, and a second end portion.
• Bit line contacts are placed on the central portions of the active patterns, spaced apart from each other in two directions.
• Separation insulating patterns are placed between adjacent bit line contacts in both directions.
• Intermediate insulating patterns are placed between the bit line contacts and the separation insulating patterns in one direction.
• Connection patterns are placed between the bit line contacts and the separation insulating patterns in the other direction.

Abstract

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURE (17994175)

Main Inventor

KEUNNAM KIM

Brief explanation

The patent application describes a semiconductor memory device with specific components and features. 

• The device includes a substrate and an insulating layer on the substrate.
• There are first and second peripheral active regions on the insulating layer, each with a first and second surface.
• A device isolation layer is present between the first and second peripheral active regions to isolate them.
• A bit line is connected to either the first surface of the first peripheral active region or the first surface of the second peripheral active region.
• A first gate insulating layer is provided on the second surfaces of the first and second peripheral active regions.
• A first peripheral gate electrode is placed on the first gate insulating layer, and a second peripheral gate electrode is placed on the second gate insulating layer.
• A contact pattern is connected to the bit line.
• Each of the first and second peripheral active regions is floated in relation to the substrate by the insulating layer.

Abstract

A semiconductor memory device includes; a substrate and an insulating layer on the substrate, first and second peripheral active regions on the insulating layer, each having a first surface and an opposing second surface, a device isolation layer between the first and second peripheral active regions to isolate the first and second peripheral active regions, a bit line connected to at least one of the first surface of the first peripheral active region and the first surface of the second peripheral active region, a first gate insulating layer provided on the second surfaces of the first and second peripheral active regions, a first peripheral gate electrode disposed on the first gate insulating layer and a second peripheral gate electrode disposed on the second gate insulating layer, and a contact pattern connected to the bit line, wherein each of the first peripheral active region and the second peripheral active region is floated in relation to the substrate by the insulating layer.

SEMICONDUCTOR DEVICE AND ELECTRONIC SYSTEM INCLUDING THE SAME (18133278)

Main Inventor

Dongjin LEE

Brief explanation

The patent application describes a semiconductor device that includes a peripheral circuit region and a memory cell region.

• The peripheral circuit region has a first substrate, circuit elements, and a first interconnection structure.
• The memory cell region has a second substrate, gate electrodes, a cell region insulating layer, and channel structures.
• The peripheral circuit region also includes lower protective layers, one of which has a hydrogen diffusion barrier layer made of aluminum oxide.
• The hydrogen diffusion barrier layer prevents hydrogen from the cell region insulating layer from reaching the circuit elements.

Abstract

A semiconductor device includes a peripheral circuit region including a first substrate, circuit elements on the first substrate, a first interconnection structure electrically connected to the circuit elements, first to fourth peripheral region insulating layer; and a memory cell region including a second substrate on the peripheral circuit region and having a first region and a second region, gate electrodes stacked on the first region, a cell region insulating layer covering the gate electrodes, channel structures passing through the gate electrodes, and a second interconnection structure electrically connected to the gate electrodes and the channel structures. The peripheral circuit region further includes first to fourth lower protective layers, at least one of the first, second, third and fourth lower protective layers includes a hydrogen diffusion barrier layer configured to inhibit a hydrogen element included in the cell region insulating layer from diffusing to the circuit elements, and including aluminum oxide.

SELF-SELECTING MEMORY DEVICES (18108117)

Main Inventor

Doyoun PARK

Brief explanation

The abstract describes a self-selecting memory device that includes multiple memory cells stacked vertically on conductive lines.

• The device consists of a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell.
• The first memory cell is composed of a first electrode, a first switching memory unit, and a second electrode stacked vertically.
• The second memory cell is composed of a third electrode, a second switching memory unit, and a fourth electrode stacked vertically.
• The first switching memory unit includes a first SSM pattern and a first nitrogen-containing pattern.
• The first SSM pattern is in contact with the upper surface of the first electrode and is made of an OTS material.
• The first nitrogen-containing pattern is in contact with the upper surface of the first SSM pattern and the lower surface of the second electrode. It is made of an OTS material doped with nitrogen.

Abstract

A self-selecting memory device includes a first conductive line on a substrate, a first memory cell on the first conductive line, a second conductive line on the first memory cell, a second memory cell on the second conductive line, and a third conductive line on the second memory cell. The first memory cell includes a first electrode, a first switching memory unit and a second electrode sequentially and vertically stacked. The second memory cell includes a third electrode, a second switching memory unit and a fourth electrode sequentially and vertically stacked. The first switching memory unit includes a first SSM pattern contacting an upper surface of the first electrode and including an OTS material, and a first nitrogen-containing pattern contacting an upper surface of the first SSM pattern and a lower surface of the second electrode and including an OTS material doped with nitrogen.