US Patent Application 18448284. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Organization Name
SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==
[[Category:EUNKYUL Oh of GWACHEON-SI (KR)]]
[[Category:YUNRAE Cho of GURI-SI (KR)]]
[[Category:TAEHEON Kim of ASAN-SI (KR)]]
[[Category:SEUNGHUN Han of SEOUL (KR)]]
SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18448284 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
- The patent application is about a semiconductor package and a method for manufacturing it. - The method involves stacking semiconductor chips using a thermo-compression bonding (TCB) method to minimize defects and increase reliability. - The semiconductor package includes an interface chip with a first test pad, a bump pad inside the first test pad, and a first through silicon via (TSV) between the first test pad and the bump pad. - There is at least one memory chip stacked on the interface chip, which includes a second test pad, a dummy pad inside the second test pad, and a second TSV between the second test pad and the dummy pad. - An adhesive layer is provided between the interface chip and the memory chip. - The first test pad and the second test pad do not have any bumps on them.
Original Abstract Submitted
The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
