US Patent Application 18100233. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract
Contents
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Organization Name
SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==
[[Category:Ki Hwan Kim of Suwon-si (KR)]]
[[Category:KYUNGHO Kim of Suwon-si (KR)]]
[[Category:KANG HUN Moon of Suwon-si (KR)]]
[[Category:CHOEUN Lee of Suwon-si (KR)]]
[[Category:Yonguk Jeon of Suwon-si (KR)]]
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18100233 titled 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Simplified Explanation
The patent application describes a semiconductor device with specific features to improve its performance. Here are the key points:
- The device includes a substrate with an active pattern, a source/drain pattern, a gate electrode, and a gate spacer.
- The source/drain pattern consists of two semiconductor layers - a first layer on the active pattern and a second layer on top of the first layer.
- The first semiconductor layer has inner sidewalls, and the distance between these sidewalls decreases as two specific portions of the layer get closer to the gate spacer.
In summary, the patent application introduces a semiconductor device design that optimizes the distance between inner sidewalls of a specific semiconductor layer, resulting in improved performance.
Original Abstract Submitted
A semiconductor device includes a substrate including an active pattern; a source/drain pattern on the active pattern; a gate electrode on the active pattern; and a gate spacer on the source/drain pattern. The source/drain pattern includes a first semiconductor layer on the active pattern and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer includes a first inner sidewall and second inner sidewall on the second semiconductor layer. A distance between the first and second inner sidewalls of the first semiconductor layer decreases according as positions of two portions of the first semiconductor layer where the distance is measured become closer to the gate spacer decreases.