US Patent Application 18067060. SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME simplified abstract

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SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Jiyoung Park of Suwon-si (KR)]]

[[Category:Yeongkwon Ko of Suwon-si (KR)]]

[[Category:Hosin Song of Suwon-si (KR)]]

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18067060 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME

Simplified Explanation

The patent application describes a semiconductor package that includes a semiconductor chip on a redistribution substrate.

  • The semiconductor package consists of a body, a chip pad, and a pillar on the chip pad.
  • It also includes a connection substrate with base layers and a lower pad on the bottom surface.
  • A first passivation layer is present between the semiconductor chip and the redistribution substrate.
  • A dielectric layer is placed between the redistribution substrate and the connection substrate.
  • The first passivation layer and the dielectric layer are made of different materials.
  • The bottom surfaces of the pillar, first passivation layer, molding layer, lower pad, and dielectric layer are all coplanar with each other.


Original Abstract Submitted

A semiconductor package includes a semiconductor chip on a redistribution substrate and including a body, a chip pad on the body, and a pillar on the chip pad, a connection substrate including base layers and a lower pad on a bottom surface of a lowermost one of the base layers, a first passivation layer between the semiconductor chip and the redistribution substrate, and a dielectric layer between the redistribution substrate and the connection substrate. The first passivation layer and the dielectric layer include different materials from each other. A bottom surface of the pillar, a bottom surface of the first passivation layer, a bottom surface of a molding layer, a bottom surface of the lower pad, and a bottom surface of the dielectric layer are coplanar with each other.

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