US Patent Application 18093568. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME simplified abstract

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SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Eunjung Kim of Suwon-si (KR)]]

[[Category:Sohyun Park of Suwon-si (KR)]]

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18093568 titled 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

Simplified Explanation

The patent application describes a semiconductor memory device with active patterns arranged in a grid-like pattern.

  • The active patterns have a central portion, a first end portion, and a second end portion.
  • Bit line contacts are placed on the central portions of the active patterns, spaced apart from each other in two directions.
  • Separation insulating patterns are placed between adjacent bit line contacts in both directions.
  • Intermediate insulating patterns are placed between the bit line contacts and the separation insulating patterns in one direction.
  • Connection patterns are placed between the bit line contacts and the separation insulating patterns in the other direction.


Original Abstract Submitted

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

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