US Patent Application 18449864. MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE simplified abstract

MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE

Organization Name

SAMSUNG ELECTRONICS CO., LTD.==Inventor(s)==

[[Category:Yongsung Cho of Hwaseong-si (KR)]]

[[Category:Min Hwi Kim of Suwon-si (KR)]]

[[Category:Ji-Sang Lee of Iksan-si (KR)]]

MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18449864 titled 'MEMORY DEVICE, OPERATION METHOD OF MEMORY DEVICE, AND PAGE BUFFER INCLUDED IN MEMORY DEVICE

Simplified Explanation

The patent application describes a memory device with a memory cell array and various components for data storage and retrieval.

• The memory device includes memory cells, data latches, a sensing latch, a temporary storage node, a switch, a first precharge circuit, and a control logic circuit.
• The data latches are connected to a sensing node and store data in a specific memory cell.
• The sensing latch is connected to the sensing node and serves as a temporary storage for data.
• The switch is connected between the sensing latch and the temporary storage node and operates based on a setup signal.
• The first precharge circuit selectively precharges a specific bit line based on the level of the temporary storage node.
• The control logic circuit controls the transfer of data between the data latches, sensing latch, and temporary storage node.
• During a dump operation, the control logic circuit transfers data from the data latches to the sensing latch while the first precharge circuit precharges the specific bit line.

Original Abstract Submitted

Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.